When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

A memory system includes a memory device and a controller. The memory device includes a memory block configured to store target data. The controller is configured to maintain the target data in a write buffer until a program operation to the memory block succeeds, update a write cache tag regarding the target data when the program operation fails and a read only mode is entered, and read the target data from the write buffer based on the write cache tag when a read command regarding the target data is received.

Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks; and a controller suitable for checking a read operation time, a read level class, an error occurrence, and an error occurrence class when performing the read operation on each of the memory blocks, classifying the memory blocks into various classes based on a result of the checking, and differently setting a durability parameter for each of the memory blocks based on a result of the classifying of the memory blocks.

Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.

A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

A storage device for preventing occurrence of a read fail has a reduced overhead. The storage device includes a memory device with a plurality of memory blocks; and a memory controller for managing a fail block and a shared block as bad blocks. The fail block is determined to be a bad block among the plurality of memory blocks. The shared block is a memory block that shares a control signal for selecting the fail block in the memory device.

A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

The disclosure is directed to a memory storage device and an automatic error repair method thereof. In an aspect, the memory storage device includes a connection interface configured to receive a write command and a word line address associated with the write command, a memory array including a memory bank which contains an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address, a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells, and a memory control circuit configured to transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

Techniques for a non-volatile memory module are provided. In an example, an apparatus can include a first memory device comprising a first type of memory media, a second memory device comprising a second type of memory media, and a controller. The controller can transfer data from the first memory device to the second memory device based at least in part on loss of system power to the apparatus while operating on power provided by a backup power source, restore the data from the second memory device to the first memory device based at least in part on the system power to the apparatus being re-established, identity chip failure of the second memory device, the chip failure based at least in part on restoring the data from the second memory device to the first memory device, and operate the apparatus based at least in part on the chip failure identified.