A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.

According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

A memory system includes a memory device including a plurality of blocks, and a controller suitable for managing the plurality of blocks by grouping the plurality of blocks into a plurality of super blocks in accordance with a predetermined condition, managing normal blocks which are not grouped into the super blocks in a replacement block pool, setting each of the plurality of super blocks that includes at least one bad block to a bad super block, and then changing each bad super block in which the at least one bad block is replaced with a normal block of the replacement block pool using replacement information to a recovery super block, wherein the replacement information includes in a bitmap indicative of whether or not an interleaving operation of each of the recovery super blocks is possible.

A memory system includes a memory device comprising a plurality of memory blocks each memory block having N word line groups, N being a natural number equal to or more than 2; and a controller suitable for: selecting bad memory blocks among the memory blocks; arranging normal word line groups of the selected bad memory blocks into one or more memory-block-word-line groups each including non-conflicting N normal word line groups; and managing each of the memory-block-word-line groups as a reused memory block, the controller manages a reused block mapping table including a plurality of entries respectively corresponding to the memory-block-word-line groups, the reused block mapping table includes a plurality of logical addresses respectively corresponding to the entries, and each of the entries includes a plurality of physical address values respectively corresponding to the selected bad memory blocks having the normal word line groups included in the corresponding memory-block-word-line group.

A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Aspects of the present disclosure configure a memory sub-system controller to generate virtual blocks using partial good blocks or portions of full blocks. The controller identifies a region of a set of memory components comprising a plurality of planes across a plurality of decks. The controller determines that a first memory block within a first deck associated with a first plane of the plurality of planes is a first partial good block (PGB), the first PGB including a portions categorized as being defective and portions categorized as being non-defective. The controller determines that a second memory block associated with a second plane is a full block (FB), the FB being categorized as non-defective. The controller generates a virtual block using the first PGB of the first memory block associated with the first plane and a portion of the FB of the second memory block associated with the second plane.

According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.