A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

A memory access controller includes a request issuing circuit to issue a user request in response to a memory request, issue a refresh request at first issuing intervals, and issue a scrubbing request at second issuing intervals; and a command issuing circuit to issue a first active to a memory via a row command bus and issue M reads to the memory via a column command bus after the first active is issued, when memory access for the user request is to be executed, issue refresh to the memory via the row command bus when the memory access for the refresh request is executed, and issue a second active to the memory via the row command bus and issues N (>M) reads to the memory via the column command bus after the second active is issued, when the memory access for the scrubbing request is to be executed.

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes memory cell array, error correction code (ECC) engine, refresh control circuit and control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine such that the ECC engine generates an error generation signal by performing ECC decoding on sub-pages in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value and provides the refresh control circuit with a first address of the first memory cell row as an error address based on the comparison. The refresh control circuit increases a number of refresh operations performed in the first memory cell row during a refresh period.

A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.

A method of operating a memory device includes; receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller for an adjacent row, relative to the target row, during a refresh operation period defining a refresh operation performed by the memory device.

Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.