Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.

Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Provided are memory devices configured to perform row hammer handling operations, and memory systems including such memory devices. An example memory device may include a memory cell array including a plurality of memory cell rows; a row hammer handler that is configured to determine whether to perform a row hammer handling operation to refresh adjacent memory cell rows adjacent to a first row that is being intensively accessed from among the memory cell rows, resulting in a determination result; and a refresh manager configured to perform either a normal refresh operation for sequentially refreshing the memory cell rows or the row hammer handling operation, based on the determination result of the row hammer handler.

A semiconductor device includes a command decoder and a period signal generation circuit. The command decoder generates a first entry command and a first exit command based on a first internal chip selection signal and a first internal control signal and generates a second entry command and a second exit command based on a second internal chip selection signal and a second internal control signal. The period signal generation circuit generates a period signal based on the first entry command, the second entry command, the first exit command, the second exit command, and the period signal.

A DRAM memory having a storage cell array is described. The storage cell array has rows and columns. The storage cell array has reserved storage cells coupled to each of the rows. The reserved storage cells to store count values that individually count activations of each of the rows.

Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.

Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.

A system and method for refreshing memory cells of a memory device includes storing each bit of a B-bit word in a different sub-array of a memory device. Each of the bits is associated with a bit position, and the memory device includes a plurality of sub-arrays. The system and method also include determining a refresh interval for a plurality of the bit positions based upon a relative importance of the plurality of the bit positions to a performance of a machine learning or signal processing task involving the B-bit word. The refresh interval is based upon a fidelity metric and a resource metric. The system and method further include refreshing the plurality of sub-arrays based upon the refresh interval determined for the plurality of bit positions, and dynamically updating the refresh interval for the plurality of bit positions upon receiving a new fidelity metric or a new resource metric.

Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.