An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

A module for multiple dies is disclosed. The module can include a group of dies that include a first die having a first voltage block and a second die having a second voltage block. The module can also include an interconnect that electrically connects the first and second dies. Power supply generation in the first die is enabled in non-active mode, while power supply generation in the second die is disabled. The power supply generation in the second die may be enabled when the second die is in active mode. The first die can send enabling signal to the second the die to enable the second die. The first die can provide supply to the second die in the non-active mode. The first die can send self-refresh timing command to the second die when the module is in a self-refresh mode.

A memory device includes a memory medium and a memory controller. The memory medium has a memory cell array and may be configured to generate a self-refresh signal, which varies based on an internal temperature of the memory medium, to control a self-refresh operation performed on the memory cell array. The memory controller may be configured to calculate an auto refresh cycle of an auto refresh control signal for controlling an auto-refresh operation of the memory medium based on the self-refresh signal.

A memory device includes a memory array, a switch device, and a controller. The switch device is arranged between a first voltage node and a second voltage node. The second voltage node is connected to the memory array. The controller is enabled to output a refresh mode signal, a refresh trigger signal, and a pre-start up signal. The memory device enters a self-refresh mode in response to the refresh mode signal. The memory device performs a self-refresh on the memory array in the self-refresh mode. In self-refresh mode, the controller outputs the pre-start up signal first prior to the refresh trigger signal to enable the switch device, so that the voltage of the second voltage node is increased to the voltage of the first voltage mode.

A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.

A modified 1C1T cell detects when the charge in the memory cell drops below a predetermined voltage due to leakage and asserts a refresh signal indicating that refresh needs to be performed on those memory cells associated with the modified 1C1T memory cell. The associated memory cells may be a row, a bank, or other groupings of memory cells. Because temperature affects leakage current, the modified memory cell automatically adjusts for temperature.

The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.

A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.