A dielectric material structure is formed laterally adjacent to a bottom portion of a bottom electrode metal-containing portion that extends upward from an electrically conductive structure that is embedded in an interconnect dielectric material layer. The physically exposed top portion of the bottom electrode metal-containing portion is then trimmed to provide a bottom electrode of unitary construction (i.e., a single piece) that has a lower portion having a first diameter and an upper portion that has a second diameter that is greater than the first diameter. The presence of the dielectric material structure prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.

A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region., a metal interconnect, and a magnetic tunneling junction (MTJ). The transistor region includes a gate over the substrate, and a doped region is at least partially in the substrate. The metal interconnect is over the doped region. The metal interconnect includes a metal via. The MTJ is entirely underneath the metal interconnect and between the doped region and the metal via, and a diameter of a bottom surface of the MTJ is greater than a diameter of an upper surface of the MTJ.

A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate, a first doped region, and a second doped region at least partially in the substrate, and a contact plug directly over the gate, a first metal interconnect composed of copper over the transistor region, and a magnetic tunneling junction (MTJ) directly over the contact plug and under the first metal interconnect.

A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

A semiconductor device is provided. The semiconductor device has a semiconductor layer including a source/drain region, a first magnetic layer over the semiconductor layer, and a first dielectric layer over the source/drain region and adjacent the first magnetic layer. The semiconductor device has a metal structure extending through the first dielectric layer, a second magnetic layer over the metal structure, and a second dielectric layer over the first magnetic layer and adjacent the first dielectric layer.