A method for manufacturing a magnetic random access memory array at a density greater than would be possible using photolithography. A hard mask material is deposited over a magnetic memory element material, and a chemical template layer such as brush or mat material is deposited over the hard mask. A mask structure is formed over the soluble polymer. The mask structure is configured with openings having a center to center spacing that is an integer multiple of a block copolymer material. The openings in the mask structure can be shrunk by depositing a spacer material. The chemical template layer is chemically patterned, such as by a quick plasma exposure and the mask is removed. A block copolymer material is then deposited over the chemical template and annealed to form block copolymer cylinders that are located over the patterned portions of the chemical template and between the patterned portions.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (STT-MRAM) devices having a magnetic tunnel junction (MTJ), and further relates to methods of fabricating the STT-MRAM devices. In an aspect, a magnetoresistive random access memory (MRAM) device has a magnetic tunnel junction (MTJ). The MTJ includes a magnetic reference layer comprising CoFeB, a magnetic free layer comprising CoFeB, and a barrier layer comprising MgO. The barrier layer is interposed between the magnetic reference layer and the magnetic free layer. The barrier layer has a thickness adapted to tunnel electrons between the magnetic reference layer and the magnetic free layer sufficient to cause a change in the magnetization direction of the variable magnetization under a bias. The MTJ further comprises a buffer layer comprising one or more of Co, Fe, CoFe and CoFeB, where the buffer layer is doped with one or both of C and N.

To accurately read data in a storage device provided with a cell having a variable resistance value. In a reference cell circuit, a resistance value changes to a predetermined initial value when an initialization signal exceeding a predetermined reversal threshold is input. A reference side signal source inputs a reference side read signal of a predetermined value not exceeding the predetermined reversal threshold to the reference cell circuit after the initialization signal is input to the reference cell circuit when there is an instruction to read with respect to a memory cell. A cell side signal source inputs a cell side read signal of the predetermined value to the memory cell after the initialization signal is input. A comparison unit compares a reference signal output from the reference cell circuit into which the reference side read signal has been input, and a cell signal output from the memory cell into which the cell side read current has been input, and acquires the comparison result as read data.

A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.

A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.

The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.

Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.

A magnetic wall utilization-analog memory element includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a magnetization fixed layer provided at a the third region through a nonmagnetic layer, and a lower electrode layer provided at a position in the third region that overlaps the magnetization fixed layer in plan view on a second surface opposite to a first surface on which the magnetization fixed layer is provided.