A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.

Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.

The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at least one data state, the later programming pass includes maintaining a count of the programming loops of the later programming pass. The later programming pass also includes inhibiting or slowing programming of the memory cells being programmed to one of the data states during a predetermined program count verify (PCV) programming loop and a PCV−1 programming loop and skipping a verify operation for all programming loops prior to a PCV+1 programming loop.

A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.

Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A method includes determining that a first programming pass of a programming operation has been performed on a memory cell of the memory component, and performing a dynamic program targeting (DPT) operation on the memory cell to calibrate a first program-verify (PV) target value that results in an adjustment to a placement of a first first-pass programming distribution and a second PV target value that results in an adjustment to a placement of a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

A memory device, a method for programming the memory device, a program verification method, and a memory system are provided. In the program verification method, an i.sup.th verification result of an i.sup.th program verification operation is obtained, where programming states verified by the i.sup.th program verification operation range from an n.sup.th state to an (n+k).sup.th state, i and n are positive integers, k is a natural number, and the (n+k).sup.th state is less than or equal to a highest programming state of the memory device; a range of programming states to be verified by an (i+1).sup.th program verification operation is determined according to a verification sub-result for the n.sup.th state and a verification sub-result for the (n+k).sup.th state in the i.sup.th verification result; and the (i+1).sup.th program verification operation is executed according to the determined range of the programming states to be verified by the (i+1).sup.th program verification operation.

A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N−K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N−K logical pages, wherein K is a positive integer and N is a positive integer greater than K.