An apparatus includes a first plane of memory cells including an associated first buffer, a second plane of memory cells including an associated second buffer. The apparatus also includes a controller configured to transfer data corresponding to a first memory state the first buffer and transfer data corresponding to a second memory state to the second buffer. The apparatus also includes state machine configured to apply program pulses to the first and second planes of memory cells. The apparatus also includes read/write circuitry configured to independently confirm that the first and second planes of memory cells have reached the first and second memory states.

A storage device includes a nonvolatile memory device including a plurality of memory cells, the memory cells divided into a plurality of pages, and a controller configured to control the nonvolatile memory device. The storage device is configured to collect two or more write data groups to be written to two or more pages, to simultaneously perform a common write operation with the two or more pages based on the two or more write data groups, and to sequentially perform an individual write operation with each of the two or more pages based on the two or more write data groups.

Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.

A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.

Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.

A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.

First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

A semiconductor memory device includes a memory cell array including a block of memory cells, gates of which are connected to a plurality of word lines, and a control unit configured to perform a writing operation in response to a command received from the outside, the writing operation including applying a program level voltage to at least two word lines at the same time.