A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.