A processing device determines that read level thresholds between first programming distributions of a second programming pass associated the memory component are calibrated. The processing device changes one or more of the read level thresholds between the first programming distributions. The processing device adjusts one or more read level threshold between second programming distributions of a first programming pass based on the change to the one or more read level thresholds between the first programming distributions.

A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.

Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. The control logic may be configured to control a program voltage to be applied to the selected word line. The control logic may be configured to control a pass voltage to be applied to an unselected word line.

A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.

A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of memory cells of the memory device. A program targeting operation is performed on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a last programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.

A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.

A semiconductor memory device includes memory cell transistors, a word line connected to the plurality of memory cell transistors, bit lines that are respectively connected to the memory cell transistors, and a control circuit. The control circuit carries out a write operation on the memory cell transistors connected to the word line by performing, in sequence, a first loop of operations, including a first program operation followed by at least one verification operation, that are carried out until all memory cell transistors targeted by the first program operation have passed the at least one verification operation, a second loop of operations, including a second program operation and no verification operation, that are carried out for a fixed number of loops and a third loop of operations, including a third program operation and no verification operation, that are carried out for a fixed number of loops.

A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.

A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.

Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory device. The semiconductor memory device may include a control logic. The control logic may be configured to control a program voltage to be applied to the selected word line. The control logic may be configured to control a pass voltage to be applied to an unselected word line.