According to one embodiment, a semiconductor storage device includes a first plane having a first plurality of memory cells, a second plane having a second plurality of memory cells, first bit lines which are connected to the first plane, second bit lines which are connected to the second plane, a plurality of first sense amplifiers which charge the plurality of first bit lines, and a plurality of second sense amplifiers which charge the plurality of second bit lines. When the first and second planes operate in parallel, a total sum of currents supplied to the plurality of first bit lines from the plurality of first sense amplifiers and currents supplied to the plurality of second bit lines from the plurality of second sense amplifiers reaches a first current value, then decreases to a second current value, and then increases to a third current value.

Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.

Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.

A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

A memory device includes a memory cell array with memory strings including a first and second select transistor and memory cells between the first and second select transistors. Each memory string has a bit line connected thereto. A different word line is connected to each of the memory cells of a memory strings. A control circuit is configured to execute a first read operation in which data is read at the same time from memory cells connected to all the bit lines and a second read operation in which data is read from memory cells connected to a first subset of bit lines and a shield voltage is applied to a second subset of bit lines in the plurality of bit lines. The controller selects the first or second read operation for execution according to the number of read voltage levels required for determining data in the memory cells.

The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a multi-page read operation on a selected memory block among the plurality of memory blocks. The peripheral circuit may select a first word line and a second word line, which are coupled to the selected memory block, and perform the multi-page read operation on the first and second word lines.

The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.

A memory system may include: a controller; and a nonvolatile memory device including memory units, and configured to perform a read operation on the memory units according to control of the controller. The controller may arrange a processing order of the memory units based on an internal read time of each of the memory units, and control the read operation according to the arranged processing order.

In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.

There are provided a memory system and an operating method thereof. A memory system includes: a memory device configured to generate first read voltages and second read voltages, based on initial read voltages and first and second offset voltages, in response to a user read command, and output first data and second data, which are acquired by performing read operations on multi-bit memory cells, based on the first read voltages and the second read voltages; and a memory controller configured to output the user read command, wherein the memory controller includes a state counter configured to count numbers of data bits respectively corresponding to a plurality of threshold voltage states from the first data and the second data, and extract numbers of memory cells respectively included in a plurality of threshold voltage regions divided by the first read voltages and the second read voltages by calculating the counted result.