A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including memory cells, each having any one of an erased state or one of a plurality of programmed states, and a memory controller configured to estimate an optimal read voltage associated with at least one of the erased state or one of the programmed states based on a threshold voltage distribution corresponding to at least one of the programmed states. The memory controller may include a threshold voltage distribution checker configured to check a first threshold voltage distribution corresponding to a first programmed state, among the programmed states, and determine an average threshold voltage of the first threshold voltage distribution, and an optimal read voltage estimator configured to estimate a second optimal read voltage corresponding to a second side of the first threshold voltage distribution.

Center error counts are determined for logical page types of the memory component. A first center error count is indicative of a number of bit errors for a first logical page type. A second center error count is indicative of a number of bit errors for a second logical page type. A modified page margin is determined based on a current page margin corresponding to the first logical page type. The current page margin corresponds to the first logical page type and is indicative of a ratio of the first center error count to the second center error count. The modified page margin is indicative of a modified ratio of a modified first center error count to the second center error count. The current page margin is adjusted corresponding to the first logical page type in accordance with the modified page margin.

Center error counts are determined for logical page types of the memory component. A first center error count is indicative of a number of bit errors for a first logical page type. A second center error count is indicative of a number of bit errors for a second logical page type. A modified page margin is determined based on a current page margin corresponding to the first logical page type. The current page margin corresponds to the first logical page type and is indicative of a ratio of the first center error count to the second center error count. The modified page margin is indicative of a modified ratio of a modified first center error count to the second center error count. The current page margin is adjusted corresponding to the first logical page type in accordance with the modified page margin.

The present disclosure is directed to read level edge find operations in a memory sub-system. A processing device receives a request to locate a first distribution edge at a target bit error rate (BER) of a first programming distribution. The processing device measures a first BER sample of the first programming distribution using a first offset value that is offset from a first center value corresponding to a first read level threshold and a second BER sample using a second offset value that is offset from the first offset value. The processing device determines that the second BER sample exceeds the target BER and the first BER sample does not exceed the target BER. The processing device determines a first location of the first distribution edge by interpolating between the first BER sample and the second BER sample.

A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

A memory system, a memory controller and a method for operating a memory system are disclosed. Specifically, by performing soft-decision decoding for data read from some of the plurality of memory cells based on a first optimum read voltage of one or more optimum read voltages, based on reliability values of one or more first threshold voltage sections, and one or more second threshold voltage sections and also based on the first and second threshold voltage sections, it is possible to provide a memory system, a memory controller and a method for operating a memory system, capable of increasing an error correction effect by soft-decision decoding even in the case where threshold voltage distributions of memory cells in which data is stored are degraded.

Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.

Techniques are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages using binary data from the memory, wherein the gap is estimated using statistical characteristics of at least one of two adjacent memory levels of the memory; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels and the gap; and updating the read threshold voltage with the adjusted read threshold voltage. Pages of the memory are optionally read at multiple read threshold offset locations to obtain disparity statistics, which can be used to estimate mean and/or standard deviation values for a given memory level. The gap is optionally estimated using the mean and/or standard deviation values.

Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including memory cells, each having any one of an erased state or one of a plurality of programmed states, and a memory controller configured to estimate an optimal read voltage associated with at least one of the erased state or one of the programmed states based on a threshold voltage distribution corresponding to at least one of the programmed states. The memory controller may include a threshold voltage distribution checker configured to check a first threshold voltage distribution corresponding to a first programmed state, among the programmed states, and determine an average threshold voltage of the first threshold voltage distribution, and an optimal read voltage estimator configured to estimate a second optimal read voltage corresponding to a second side of the first threshold voltage distribution.