Center error counts are determined for logical page types of the memory component. A first center error count is indicative of a number of bit errors for a first logical page type. A second center error count is indicative of a number of bit errors for a second logical page type. A modified page margin is determined based on a current page margin corresponding to the first logical page type. The current page margin corresponds to the first logical page type and is indicative of a ratio of the first center error count to the second center error count. The modified page margin is indicative of a modified ratio of a modified first center error count to the second center error count. The current page margin is adjusted corresponding to the first logical page type in accordance with the modified page margin.

A computer-implemented method, according to one approach, includes: using a first calibration scheme to calibrate the given page in the block by calculating a first number of independent read voltage offset values for the given page. An attempt is made to read the calibrated given page, and in response to determining that an error correction code failure occurred when attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block. The second calibration scheme is configured to calculate a second number of independent read voltage offset values for the given page. An attempt to read the recalibrated given page is also made. In response to determining that an error correction code failure did occur when attempting to read the recalibrated given page, one or more instructions to relocate data stored in the given page are sent.

The present disclosure relates to a method and apparatus for determining a reference voltage. The method may comprise: reading data from a first flash memory page by using a plurality of different reference voltages, and taking, as a first target reference voltage, one of the plurality of different reference voltages at which the first number of erroneous bits of the data that is read reaches a convergence value, wherein the first flash memory page is any one of a plurality of flash memory pages of a flash memory block to be tested; adjusting the first target reference voltage to obtain a plurality of second target reference voltages; and reading data from the plurality of flash memory pages of the flash memory block by using the plurality of second target reference voltages, and taking, as a target reference voltage, one of the plurality of second target reference voltages at which the second number of erroneous bits of the data that is read is the smallest. By the method, the present disclosure can determine a current actual reference voltage of a flash memory block, thereby the flash memory block may operate normally and the data may be accurately read.

Center error counts are determined for logical page types of the memory component. A first center error count is indicative of a number of bit errors for a first logical page type. A second center error count is indicative of a number of bit errors for a second logical page type. A modified page margin is determined based on a current page margin corresponding to the first logical page type. The current page margin corresponds to the first logical page type and is indicative of a ratio of the first center error count to the second center error count. The modified page margin is indicative of a modified ratio of a modified first center error count to the second center error count. The current page margin is adjusted corresponding to the first logical page type in accordance with the modified page margin.

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense a state of the memory cell, a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, one or more of the plurality of sense components may sense the charge with one of a variety of sensing schemes. Based on the charge being transferred using the charge transfer device and each sense component sensing the charge, a logic state associated with the memory cell may be determined. The number of sensed states may be correlated to the number of sense amplifiers. The ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than one.

A data sensing device and a data sensing method thereof are provided. The data sensing device includes a compensation signal generator, a weighting operator and an arithmetic operator. The compensation signal generator receives a basic input signal and a plurality of reference weighting values, and generates a compensation signal according to the basic input signal and the reference weighting values. The weighting operator has a plurality of memory cells, performs a writing operation on the memory cells according to the weighting values based on address information, and the weighting operator generates an output signal by the memory cells by receiving a plurality of input signals. The arithmetic operator performs an operation on the output signal and the compensation signal to generate a compensated output signal.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.