The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and a quantizing circuit. The quantizing circuit includes a combination circuit configured to combine an analog input signal with an analog feedback signal to produce a delta signal. The quantizing circuit also includes an integrator configured to receive and integrate the delta signal to produce a sigma signal. The quantizing circuit also includes an analog-to-digital converter configured to receive the sigma signal and compare the sigma signal with a reference signal to produce a digital output signal.

A storage device includes a non-volatile memory including a plurality of blocks, a buffer memory that stores a plurality of on-cell counts, which are generated by reading memory cells connected to a plurality of reference word lines of the plurality of blocks by using a read level, and an artificial neural network model, and a controller that inputs an on-cell count corresponding to a target block among the plurality of on-cell counts and a number of a target word line of the target block to the artificial neural network model, and infers a plurality of read levels for reading data of memory cells connected to the target word line using the artificial neural network model.

Techniques are provided for tuning the voltages of a circuit for reading a memory cell capable of storing three or more logic states. To read the memory cell, a charge may be transferred between a digit line and a sense component using a charge transfer device. The gate of the charge transfer device may initially be biased to a first voltage and subsequently tuned to a second voltage to optimize the sense window. After biasing the gate of the charge transfer device to the second voltage, the memory cell may discharge its charge onto the digit line, which may result in the digit line being biased to a third voltage. Based on whether the third voltage exceeds the second voltage, the charge transfer device may transfer the charge associated with the memory cell.

An method of operating a nonvolatile memory device including a plurality of memory cells comprises receiving a read command from an external device, in response to the read command, performing, based on a reference voltage, a first cell counting operation with respect to the plurality of memory cells, adjusting at least one read voltage of first through nth read voltages (where n is a natural number greater than 1) based on a first result of the first cell counting operation, and performing, based on the adjusted at least one read voltage, a read operation corresponding to the read command with respect to the plurality of memory cells.

A semiconductor memory device includes a plurality of memory cells that include one or more pairs of reference cells that store reference data, and a circuit peripheral thereto. The memory cells are commonly connected to a word line and connected to a plurality of bit lines, respectively. The circuit is configured to apply a read voltage to the word line, cause sense nodes of bit lines connected to the reference memory cells of each pair to be electrically connected to each other, determine whether or not each of the plurality of reference memory cells is ON or OFF based on a voltage at a sense node of each of the plurality of bit lines, and update the read voltage based on the number of reference memory cells determined to be ON and the number thereof determined to be OFF.

A nonvolatile memory device includes: a plurality of first reference cells that are connected in parallel, and are in an intermediate state between an erased state and a programmed state; a first current mirror circuit that generates a first mirror current proportional to a sum of currents flowing through the plurality of first reference cells in a state in which the plurality of first reference cells are selected; and a sense amplifier that, in a readout mode, generates a reference current based on at least the first mirror current, and reads out data stored in a memory cell by comparing a current flowing through the memory cell with the reference current.

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.