A storage system has a memory with a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block. The storage system repurposes the partially-bad SLC block as a non-volatile read cache for data stored in the MLC block (e.g., cold data that is read relatively frequently) to improve performance of host reads. Because the original version of the data is still stored in the MLC block, the original version of the data can be read if there is an error in the copy of the data stored in the partially-bad SLC block, thus avoiding the need for extensive error-correction handling to account for the poor reliability of the partially-bad SLC block.

A storage system has a memory that is organized in wordlines. Each wordline has a number of strings. A controller in the storage system changes, in each of the wordlines, which of the strings is a last string programmed. Doing so can unmask a program disturb error when triple-level cells in the memory are used as pseudo-multi-level cells. By unmasking the program disturb error, the controller can detect and correct the error.

Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.

A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.

A storage device may include; a non-volatile memory including a first memory region including first memory cells having a first data storage capacity, a second memory region including second memory cells having a second data storage capacity greater than the first data storage capacity, and a third memory region including third memory cells having a third data storage capacity greater than the second data storage capacity, and a storage controller configured to receive a request, data, and storage time information associated with the data from a host, and program the data in a selected one of the first memory region, the second memory region and the third memory region in response to the request and on the basis of the storage time information.

An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

A data storage device monitors a storage media temperature and adjusts data storage operations of the storage device based on the monitored and/or a predicted future temperature of the storage media. In one approach, data is stored in a first mode (e.g., a TLC mode) in a non-volatile storage media. One or more temperatures associated with the non-volatile storage media are monitored using at least one sensor to collect sensor data. The manner of storage of the data in the storage device is adjusted based on the collected sensor data. The adjusting comprises compressing the data to provide compressed data, and storing the compressed data in a second mode (e.g., an SLC mode) in the non-volatile storage media.

The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.