Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

A control method applied in a storage device for dynamically adjusting a ratio of single-level cell (SLC) blocks and three-level cells (TLC) blocks is provided. A selection input is received. The number of SLC blocks and TLC blocks of a flash memory are adjusted according to the selection input. In response to the storage device being reset, the number of SLC blocks and TLC blocks of the flash memory are re-adjusted.

Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage differences in one or more storage characteristics for blocks of a non-volatile memory medium within one or more established limits. A block classification module is configured to group blocks of a non-volatile memory medium based on one or more other storage characteristics. A configuration parameter module is configured to use a configuration parameter for at least one group of blocks based on a grouping. A configuration parameter update module is configured to update a configuration parameter for at least one group in response to a change in one or more managed storage characteristics.

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.

A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.

Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.

A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.