Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation.

Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells and a plurality of page buffers. The plurality of page buffers may be coupled to the plurality of memory cells through a plurality of bit lines. The plurality of page buffers may perform a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage, the bit line precharge operation being included in a memory operation of detecting threshold voltages of the first memory cells, and clamp potentials of second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the memory operation.

A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2.sup.N−1, and Ln being one of 2.sup.N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

A memory system in accordance with an embodiment may include a memory chip and a controller. The memory chip may store data in a plurality of logical pages by performing a sensing operation on a selected page in response to commands and performing an output operation of the data. The controller may transmit the commands to the memory chip so that a part of the sensing operation and a part of the output operation are simultaneously performed.

A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.

Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.

A method for a pre-lockout read for a reverse order read operation with lockout mode is disclosed. The method comprises: performing a pre-lockout read at a first sensing level to determine which memory cells of the set of memory cells are on in response to the first sensing level being applied to a selected word line; performing a first sensing operation on the selected word line at a second sensing level including sensing memory cells of the set of memory cells determined to be off in response to the pre-lockout read; and performing a second sensing operation on the selected word line at a third sensing level including sensing memory cells of the set of memory cells determined to be on in response to the pre-lockout read, where the first sensing level is of a value between the second sensing level and the third sensing level.

A nonvolatile memory device includes; a memory cell array including a meta data region storing chip-level information, control logic identifying a target cell in response to a command, machine learning (ML) logic inferring an optimum parameter based on the chip-level information and physical information associated with the target cell applied as inputs to an artificial neural network model, and a buffer memory configured to store weight parameters of the artificial neural network model.

Provided herein may be a memory device having a page buffer. The memory device may include a memory cell configured to store data, and a page buffer coupled to the memory cell through a bit line and configured to store data to be used in a program operation and to precharge the bit line to a first precharge voltage or a second precharge voltage lower than the first precharge voltage depending on the data during a program verify operation performed in the program operation.

A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.