According to one embodiment, a memory device is configured to execute an efficient read operation is provided. The memory device includes a plurality of memory cells, a word line, and a controller. Each of the memory cells stores first to fifth bit data based on the threshold voltage. The memory cells store a first page to a fifth page respectively corresponding to the first bit data to the fifth bit data. A word line is coupled to the memory cells. A controller executes a read operation for reading data from the memory cells by applying a read voltage to the word line. Numbers of times the controller applies read voltages different from one another to the word line in read operations for the first page to the fifth page are 7, 6, 6, 6, and 6, respectively.

According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.

A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

Provided are several preferred options of 3D hierarchical NAND arrays being formed in a (2D DL//3D LBL).sub.⊥(3D CSL//3D WL) scheme and their associated 2D PBs are preferably formed right below the 3D array but on the reversed side of Psub so that the large silicon areas of most 2D peripheral circuits can be saved and the various 3D nLC NAND operations can be performed in more powerful pipeline and concurrent manner with a dramatic reduction in latency and power consumption.

The preferred various 3D hierarchical NAND memories comprise a plurality of divided 3D sub-arrays for nLC storage, a plurality of 3D N-bit Cstring-based DCRs with minimum memory capacity to store 3×2n pages of program data when a 3-WL rotational nLC program scheme is adopted, and a plurality of distributed N-bit PBs with same number of LBL lines.

Each hierarchical 3D array comprises a plurality of 3D LGs and each LG comprises a plurality of 3D blocks connected by N local 3D LBL metal lines and 3D CSL lines and each block further comprises N strings without a need of extra local precharge line of LGps lines as disclosed in prior granted patents.

More number of distributed N-bit PBs would allow more powerful and flexible concurrent operations to be performed at the expense of taking larger silicon area in reversed side of Psub. By contrast, less number of distributed N-bit PBs would allow less powerful and flexible concurrent operations to be performed with a tradeoff of saving more silicon area in the reversed side of Psub. For performing any concurrent 3D NAND operation, a minimum two N-bit PB and 3×2n N-bit DCRs are required. Each N-bit SA comprises at least n+1 N-bit latches.

Each bit of PB comprises one SA and one nLC-latch circuit. N-bit SA further comprises one N-bit Current-sensing circuit for performing ABL program, ABL page data loading in each N-bit CLBLs, ABL program-verify, ABL read on each 3D sub-array and ABL Write-back to each N-nit Cstring-based DCRs, and one N-bit Voltages-sensing circuit for performing HBL Recall from each page of selected Cstring-based N-bit DCR to N-bit PB. The operations of the 3D hierarchical NAND and Cstring-based DCR arrays and their associated distributed PBs can be performed in both concurrent and pipeline manners, regardless of a 2-poly floating-gate 3D cell or a 1-poly charge-trapping 3D cell, regardless of GIDL or FN-tunneling erase scheme, regardless of SLC, MLC, TLC and XLC storage types.

A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.

A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.

Provided herein may be a memory device having a page buffer. The memory device may include a memory cell configured to store data, and a page buffer coupled to the memory cell through a bit line and configured to store data to be used in a program operation and to precharge the bit line to a first precharge voltage or a second precharge voltage lower than the first precharge voltage depending on the data during a program verify operation performed in the program operation.

An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

A nonvolatile memory device includes a memory cell region and a peripheral circuit region disposed below the memory cell region. The peripheral circuits include a page buffer, a row decoder, and other peripheral circuits, wherein the page buffer is included in a page buffer block disposed on a lower surface of the first semiconductor substrate to be distinguished from other circuits included in the peripheral circuit region in a first direction perpendicular to an upper surface of the first semiconductor substrate, is connected to the memory cell region through a connection portion penetrating through the first semiconductor substrate, and includes a plurality of vertical transistors each defined by a source region, a channel region, and a drain region stacked in sequence in the first direction.