A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.

According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches.

Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.

A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N−K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N−K logical pages, wherein K is a positive integer and N is a positive integer greater than K.

A page buffer circuit includes a sensing latch circuit and a caching latch circuit. The sensing latch circuit is configured to receive and sense data that is stored in a memory cell during a normal read operation. The caching latch circuit is configured to receive and sense the data that is stored in the memory cell during a suspend read operation.

According to one embodiment, a memory device is configured to execute an efficient read operation is provided. The memory device includes a plurality of memory cells, a word line, and a controller. Each of the memory cells stores first to fifth bit data based on the threshold voltage. The memory cells store a first page to a fifth page respectively corresponding to the first bit data to the fifth bit data. A word line is coupled to the memory cells. A controller executes a read operation for reading data from the memory cells by applying a read voltage to the word line. Numbers of times the controller applies read voltages different from one another to the word line in read operations for the first page to the fifth page are 7, 6, 6, 6, and 6, respectively.