Methods, systems, devices, and computer-readable media are disclosed for performing read disturb management of a memory device. In one embodiment, a method is disclosed comprising retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.

A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.

A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.

An operation method of a nonvolatile memory device which includes a memory block having wordlines includes performing an erase on the memory block, performing a block verification on the memory block by using a 0-th erase verification voltage, performing a delta verification on the memory block by using a first erase verification voltage different from the 0-th erase verification voltage when a result of the block verification indicates a pass, and outputting information about an erase result of the memory block based on the result of the block verification or a result of the delta verification. The delta verification includes generating delta counting values respectively corresponding to wordline groups by using the first erase verification voltage, generating a delta value based on the delta counting values, and comparing the delta value and a first reference value.

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

Aspects of a storage device including a controller are provided which recovers misidentified bad blocks that fail to erase due to charge leakage from a previously programmed open block. The controller programs an open block, and attempts to erase a plurality of closed blocks following the programming of the open block. When the closed blocks fail to erase, the controller marks the closed blocks as bad blocks. The controller then determines whether a number of consecutive erase failures after programming the open block meets a threshold, in response to which the controller resets a die including the closed blocks and reattempts to erase the closed blocks. The controller then unmarks as bad blocks the closed blocks which successfully erased in response to the re-attempt.

Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.

A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.