Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

A method, computer system, and computer program product for operating a computer system to carry out a data dump of a data image of memory contents. Computer operations are temporarily suspended to service the dump request in order to dump the volatile memory contents required for the data image and to generate a record of the non-volatile memory pages which need to be dumped. Computer operations are then resumed under supervision of a monitoring process which screens access requests to the non-volatile memory against the dump record. A request relating to a page contained in the dump record is acted upon by writing the contents of that page to the dump storage space, so the page contents is dumped before it is modified. The dump record in continually updated to keep track of what is still outstanding to complete the dump until such time as the dump is complete.

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Provided herein may be a method of operating a semiconductor memory device. The method of operating a semiconductor memory device may include programming selected memory cells with first page data, and programming the selected memory cells with second page data and programming a flag cell with flag data according to a foggy-fine programming scheme. The flag data may indicate whether data programmed according to the program operation is the first page data or the second page data. An operation of programming the flag cell with the flag data may be initiated after foggy programming of the second page data is completed.

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

A memory system includes: a memory device; and a non-erase block management device suitable for determining, when an erase operation is performed on a first memory block included in the memory device, whether to perform a read operation on a second word line of a second memory block, according to a location of a first word line, which is a target word line for a read operation on the second memory block, wherein the second word line includes a target word line for a dummy read operation.

A memory device includes a memory cell array including a plurality of word lines, at least one select line provided above the plurality of word lines, and a channel region passing through the plurality of word lines and the at least one select line, the plurality of word lines and the channel region providing a plurality of memory cells, and a controller. The controller is to store data in a program memory cell among the plurality of memory cells by sequentially performing a first programming operation and a second programming operation, and to determine a program voltage input to a program word line connected to the program memory cell, in the first programming operation, based on information regarding the program memory cell.

Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data n the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.