According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory array, the storage device to program, during a first programming pass, a plurality of cells of a first wordline of the NAND flash memory array to store a first page of data; initiate a read of the first page of data prior to completion of loading of a second page of data to be programmed during a second programming pass; and program, during the second programming pass, the plurality of cells of the first wordline of the NAND flash memory array to store the first page of data and the second page of data.

Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.

An electronic device includes memory devices, and a memory controller configured to provide program commands instructing to store data in the memory devices, each of the memory devices including a memory block including a plurality of memory cells, a peripheral circuit configured to perform a first program operation and a second program operation of storing the data in select memory cells which are memory cells selected from among the plurality of memory cells, in response to the program command, and a program operation controller configured to control the first program operation and the second program operation, the first program operation performed using one logical page data among page data to be stored in the select memory cells, and the second program operation performed using remaining logical page data except for the one logical page data among the page data.

To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

Inventive aspects include a memory device having one or more memory pages including a plurality of memory cells each having a plurality of programmable state levels. The memory device includes a memory control logic section including a program logic section and page-level reprogram state metadata. The program logic section may program the plurality of memory cells dependent on the page-level reprogram state metadata. The program logic section may program a first state level, a second state level, and a third state level of each of the memory cells in consecutive programming operations of the plurality of memory cells dependent on the page-level reprogram state metadata, without requiring any erase operations or read operations during or between the programming operations. Any combination of 1's bit, 2's bit, 4's bit, 8's bit, or 2.sup.(N−1)'s bit locations can be written to in a single program operation, as long as the lower order bits are not re-used for later writes, and proper state keeping is kept.