A smart self-repair device and method of self-repairing a package is disclosed. The smart self-repair device may include a fuse array configured to store information regarding respective bits of a fail address in fuses. The smart self-repair device may include a self-repair control circuit configured to control repairing of not only a target mat in which a fail occurs, but also adjacent upper and lower mats sharing a sense amplifier along with the target mat, and to output fail address information corresponding to a fail mode, and row fuse set information or a column fuse set information. The smart self-repair device may include a data control circuit configured to output repair information to the fuse array based on the fail address information and the row fuse set information or the column fuse set information, and may include a control circuit configured to control a rupture operation of the fuse array.

A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.

A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.