Patent classifications
G01R1/0416
TEST CIRCUIT IN DIE STACK
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
Configuration method of configuring a measurement instrument
A configuration method of configuring a measurement instrument is described. The measurement instrument comprises at least one measurement port being connectable to at least one device under test. The measurement instrument further comprises a control circuit and a measurement circuit. The control circuit is connected to the measurement circuit. The measurement circuit is connected to the at least one measurement port. The configuration method comprises the steps of: comparing a loaded test routine with configuration data stored in the measurement instrument, determining whether the test routine is performable by the measurement instrument based on the comparison of the test routine with the configuration data; and adapting the loaded test routine based on the configuration data.
Precision, high bandwidth, switching attenuator
An apparatus includes a fixed substrate having at least two contact structures, a movable substrate having at least two electrically conductive paths, a housing containing the fixed substrate and the movable substrate, a plurality of connectors in the housing, each connector connecting to one of the at least two contact structures to connect to ground and a spring contact, the plurality of connectors arranged to connect to at least one of the conductive paths depending upon a position of the movable substrate, and a motorized stage in the housing to move the movable substrate to align one of the at least two conductive paths to form a connection between two of the connectors. The apparatus may be part of a test and measurement instrument, and a method of operating the apparatus is also included.
Connection jig for testing small connector
A connection jig comprises: a first output terminal and a second output terminal for connecting to signal lines of the measuring instrument; a jig body having the shape of a plate-shaped block, into which the small connector can be inserted, and having an insertion hole penetrating from the upper surface to the lower surface of the plate-shaped block; a printed circuit board for a jig that can be inserted into the lower surface of the plate-shaped block and has a signal pattern that can be electrically connected to the small connector accommodated in the insertion hole; a lower cover detachably attached to the lower surface of the jig body and fixing the printed circuit board for the jig to the jig body; and an upper cover attachable to and detachable from the upper surface of the jig body and fixing the small connector to the jig body.
Inspection Apparatus
An inspection apparatus includes: a wafer fixing mechanism unit configured to support a wafer including a device under test having an electrode terminal on one surface and an optical input/output unit on the other surface; an optical probe provided on the one surface side of the wafer, and configured to transmit/receive an optical signal to/from the optical input/output units of the device under test; a conductive probe provided on the other surface side of the wafer, and electrically contacted with the electrode terminal of the device under test; and a wafer non-contact state maintaining unit which is a planar member having an opening in a center portion, and configured to maintain a distance from the wafer by intaking/exhausting pressurized air with respect to the wafer and to enable access to the device under test on the wafer through the opening.
TEST FIXTURE, CALIBRATION SETUP AND METHOD OF CALIBRATING A TEST AND/OR MEASUREMENT INSTRUMENT
The present disclosure relates to a test fixture for being connected to a calibration device for calibrating a test and/or measurement instrument. The test fixture includes a probing point configured to receive a calibration signal while being in contact with a probe. The test fixture has a memory configured to store fixture data related to the probing point. Further, a calibration setup and a method of calibrating a test and/or measurement instrument are described.
PROBE ASSEMBLY, PROBE SYSTEM, METHOD FOR MAINTAINING ALIGNMENT, AND SEMICONDUCTOR DEVICE TESTED
A probe assembly includes at least one probe, a probe holder, and an adaptor. The probe is configured to include a probe tip and has a first a first length and a first coefficient of thermal expansion. The probe holder is configured to hold the probe, and has a second length and a second coefficient of thermal expansion. The adaptor is configured to attach to the probe holder, and has a third length and a third coefficient of thermal expansion. Furthermore, the first coefficient of thermal expansion is a positive coefficient of thermal expansion, and one of the second coefficient of thermal expansion and the third coefficient of thermal expansion corresponds to either: a material having a negative coefficient of thermal expansion; or a composite structure comprising a positive thermal expansion material and a negative thermal expansion material, arranged such that the overall thermal expansion characteristic is stable.
EDGE CARD CONNECTOR WITH PROBE-ACCESS APERTURES
An edge-card connector mounted to a PCB includes a housing that retains contact terminals arranged in differential pairs for mating via a card-mating slot. The housing further defines, on an exterior face distinct from the slot, probe-access aperture sets aligned to the differential pairs. Each set has two apertures with spacing and orientation registered to the pair and sized to receive probe tips, guiding the tips into contact with corresponding terminals while preventing contact with neighboring terminals to enable in-situ measurement.
Integrated circuit package including an integrated shunt resistor
An integrated circuit (IC) package includes a partial leadframe including (a) a shunt resistor leadframe element including a pair of shunt resistor contacts and a shunt resistor conductively connected between the pair of shunt resistor contacts and (b) at least one external contact leadframe element separate from the shunt resistor leadframe element, the at least one external contact leadframe element allowing external contact to the IC package. The IC package also a mold encapsulation formed over the shunt resistor leadframe element, wherein the pair of shunt resistor contacts are externally contactable through the mold encapsulation.
TEST JIG
A test jig includes a first port, a second port, a measurement conductor, a current transformer, and a current output port. A first end of the first port is electrically connected to a first device. A first end of the second port is electrically connected to a second device. Two ends of the measurement conductor are connected with a second end of the first port and a second end of the second port respectively. The current transformer is electrically connected with the measurement conductor in parallel. The current output port is electrically connected to an output end of the current transformer and is configured to output a to-be-tested current. A test efficiency of the test jig is improved.