A testing device and probe elements thereof are provided. The testing device includes a circuit substrate, a plurality of probe elements, a first housing and a second housing. The plurality of probe elements are independent of each other and arranged at fixed intervals. Each probe element comprises a body, a first contact section and a second contact section. The body is provided with a plurality of strip-shaped perforations, and the body includes a first lateral side and a second lateral side opposite to each other. The first contact section is connected to the first lateral side, and the second contact section is connected to the second lateral side. The extension direction of the first contact section relative to the body and the extension direction of the second contact section relative to the body are distinct from each other.

An land grid array (LGA) or hybrid land grid array (HLGA) includes a socket housing and a plurality of electrical contacts. The socket housing is made of a first material that defines a first dielectric constant. The plurality of electrical contacts extends through the socket housing to electrically couple a printed circuit board on a first side of the socket housing to a processor on a second side of the socket housing. A coating of a second material that defines a second dielectric constant that is higher than the first dielectric constant covers surfaces of a subset of the plurality of electrical contacts.

Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.

A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT; and a lid member that covers the DUT and is attached to the carrier body. The lid member includes: a plate-like main body; and a pusher protruding from the main body in a convex shape.

The present invention relates to a plate-shaped connection system for the connection of two test units, such as for example a testing device (tester) and a handling device (handler). The handling device serves for the feeding of semiconductor elements to the tester of a test system, for the testing of such semiconductor elements. The plate-shaped connection system comprises a master frame and an insert frame. The master frame is designed for connection with a first of the two test units and one or more docking elements are provided for releasable connection with the other second test unit. The insert frame is designed that it may be connected to the master frame. The insert frame extends inwards from an inner edge of the master frame, wherein the insert frame has mounting elements for the mounting of a test board.

A ceramic containing, in mass %: Si.sub.3N.sub.4: 20.0 to 60.0%, ZrO.sub.2: 25.0 to 70.0%, at least one selected from SiC and AlN: 2.0 to 17.0%, where AlN is 10.0% or less, at least one selected from MgO, Y.sub.2O.sub.3, CeO.sub.2, CaO, HfO.sub.2, TiO.sub.2, Al.sub.2O.sub.3, SiO.sub.2, MoO.sub.3, CrO, CoO, ZnO, Ga.sub.2O.sub.3, Ta.sub.2O.sub.5, NiO and V.sub.2O.sub.5: 5.0 to 15.0%, wherein Fn calculated from the following equation (1) satisfies 0.02 to 0.40. This ceramic can be laser machined with high efficiency.

Fn=(SiC+3AlN)/(Si.sub.3N.sub.4+ZrO.sub.2)  (1)

A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT; and a lid member that covers the DUT and is attached to the carrier body. The carrier body has contactors provided to correspond to terminals of the DUT, external terminals electrically connected to the contactors, and a first through-hole for positioning that is provided to face the DUT. The first through-hole penetrates the carrier body so that a part of the DUT is seen from an outside through the first through-hole.

A probing device includes a probe station having a platform with an opening; a manipulator on the platform and having a probe; a test head; and a socket disposed on the test head and configured to support a DUT. The test head has a moving part configured to allow the DUT to be moved with respect to the probe station.

A method and an apparatus for testing a semiconductor device are provided. The apparatus includes: one or more ground contacts configured for coupling to one or more ground terminals of the semiconductor device respectively; and a detection module having one or more inputs coupled to the one or more ground contacts respectively, and configured to detect electrical conditions at the one or more ground contacts; wherein, when the semiconductor device is mounted on the test apparatus, a first signal is generated at an output of the detection module if all of the one or more ground contacts are coupled to the one or more ground terminals of the semiconductor device, and a second signal different from the first signal is generated at the output of the detection module if at least one of the one or more ground contacts is not coupled to the one or more ground terminals.