A wafer inspection system is provided. The wafer inspection system includes: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.

The method may be used for measuring an electric property of a magnetic tunnel junction used in an embedded MRAM memory for example. The method uses a multi point probe with a plurality of probe tips for contacting a designated area of the test sample, which is electrically insulated from the part of the test sample which is to be tested. Electrically connections are placed underneath the magnetic tunnel junction and goes to the designated area.

In one embodiment, the present invention includes an interface assembly for a vertical probe contactor. The interface assembly comprises a base board, a mounting board, a depth adjust plate, and an interface apparatus. The depth adjust plate is between the base board and the mounting board, and the interface apparatus is mounted to the mounting board. The interface apparatus is configured to receive the vertical probe contactor through an opening in the base board and a corresponding opening in the depth adjust plate. A thickness of the depth adjust plate defines a vertical distance between a wafer side of the base board and a plurality of probe tips of the vertical probe contactor.

A semiconductor device is provided. The semiconductor device includes a first test pad and a plurality of second test pads. The first test pad includes a central portion and a plurality of peripheral portions. The plurality of peripheral portions are disposed adjacent to edges of the central portion. The plurality of peripheral portions are not in contact with each other and with the central portion. The first test pad has a plurality of detection directions, and at least one of the plurality of peripheral portions is disposed in one of the plurality of detection directions. Each of the plurality of second test pads is electrically connected to one of the plurality of peripheral portions through a first connection trace.

An aligning mechanism according to one aspect of the present disclosure includes a mounting table on which a substrate is placed; a holding section configured to hold the mounting table from below; lifting pins configured to raise or lower the mounting table with respect to the holding section; and an aligner configured to support the holding section from below, and to change a position of the holding section relative to the lifting pins. In the holding section and the aligner, through-holes are formed such that the lifting pins can penetrate the through-holes.

A semiconductor device for testing a semiconductor wafer includes a circuit board, a probe disposed below the circuit board and facing the semiconductor wafer, an integrated substrate disposed between the circuit board and the probe, and signal-transmitting module disposed on the circuit board and next to the integrated substrate. The probe is electrically coupled to the circuit board through the integrated substrate, and the signal-transmitting module transmits a test signal to the probe through the integrated substrate and the circuit board to perform a test to the semiconductor wafer. Another semiconductor device including the integrated substrate and a manufacturing method thereof are provided.

A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.

A test probe assembly for determining the integrity of a test pad of a semiconductor wafer. The test probe assembly includes a probe card, a plurality of test probes mounted to the probe card, a fiber optic lead mounted to each test probe and arranged to direct incident light toward individual test pads of the semiconductor wafer and a plurality of photodetectors arranged about the probe card. Individual photodetectors are configured to receive light reflected off a dielectric coating of the test pad corresponding to a first set of light rays emitted by the test pad and configured to receive light reflected off a metallic base of the test pad corresponding to a second set of light rays emitted by the test pad, and to generate first and second output signals associated with the first and second sets of light rays to create image data of the individual test pads.

The present disclosure provides a probe apparatus, including a circuit board, a flexible interconnect substrate, at least one probe, and a supporting element. The circuit board includes tester contacts. The flexible interconnect substrate has a first surface and an opposing second surface. The flexible interconnect substrate is electrically coupled to the circuit board. The probe is disposed in the first surface of the flexible interconnect substrate. The probe is electrically coupled to the flexible interconnect substrate, and the probe is configured to electrically contact a device under test. The supporting element is adhered to the second surface of the flexible interconnect substrate. The supporting element is disposed between the flexible interconnect substrate and the circuit board.

A thermally conductive material, device, and method for predictably maintaining the temperature state and condition of the contact elements and support hardware of a tester interface, such as a probe card, for a testing apparatus, such as automated test equipment (ATE), that has a predetermined configuration applicable for the particular pin contact elements, thermal conditions. The thermally conductive device also has a substrate having a predefined form factor which can be readily introduced into the testing apparatus during normal testing operations. Unlike a patterned substrate that is constrained to specific probe element layouts, the unpatterned surface of the heat conductive device facilitates use with multiple probe card designs within numerous automated test equipment (ATE) tools.