Current sensing in an on-die direct current-direct current (DC-DC) converter for measuring delivered power is disclosed. A DC-DC converter converts input voltage to output current at an output voltage coupled to a load circuit. The DC-DC converter includes a high side driver (HSD) circuit to drive the output current in a first stage, and a low side driver (LSD) circuit to couple the power output to a negative supply rail (GND) in a second phase, output current being periodic. The DC-DC converter includes an amplifier circuit to equalize an output voltage and a mirror voltage. Based on the mirror voltage, the current sensing circuit generates mirror current that corresponds to driver current. The mirror current can be measured as a representation of the output current delivered to the load circuit. A plurality of the DC-DC converters can provide multi-phased current to the load circuit for providing power to the load circuit.

Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.

A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

Circuits and methods that use harvested electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0.fwdarw.1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1.fwdarw.0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0.fwdarw.1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

An embodiment of the present invention provides a load sharing control device included in each of multiple power supply devices connected to a load in parallel, the load sharing control device comprising: a first control unit for generating a first control signal which controls an output current of a power supply device, by using the output current of the power supply device and a current of a load share bus; and a second control unit for generating a second control signal which controls an output voltage of the power supply device, by using a target voltage of the power supply device, a feedback voltage received as feedback from the output voltage of the power supply device, and a control voltage according to the first control signal of the first control unit, wherein the first control unit generates the first control signal so that the output current is identical to the current of the load share bus, and limits the output current to a threshold current or less.

A system-on-a-chip (“SoC”) in a computing device may be provided with a power delivery network (“PDN”) self-test to detect marginal PDN performance. In the self-test, a current surge may be generated on power supply connections of logic circuit blocks. Voltage monitors may measure voltage droop on the power supply connections responsive to the current surge. Voltage droop measurements may be compared with thresholds. An action, such as generation of an alert, may be performed if a voltage droop measurement exceeds a threshold.

A detection result recording and outputting device of an IC is operable to record and output detection results at different speeds respectively. The device includes a sensing circuit, a decision circuit, a storage circuit, and a control circuit. The sensing circuit detects the variation in a characteristic of a target circuit and generates detection results at a first speed. The decision circuit receives the detection results and generates a trigger signal or changes its level when finding that a detection result satisfies a predetermined condition. The control circuit writes the detection result and subsequent (N−1) detection results into the storage circuit at a second speed according to the trigger signal, and then reads out the detection results from the storage circuit at a third speed and outputs them at a fourth speed. The second speed is not higher than the first speed, but higher than the fourth speed.

A power circuit includes at least one power detector coupled to both a first power voltage input via a pin or pad and a second power voltage supplied into a component, and configured to output a sensed power voltage changed from the first power voltage in response to a drop of the second power voltage, and a comparator configured to compare the sensed power voltage with a reference voltage to output a power sensing result.

An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.