An apparatus for detecting an anomaly in an electronic system embodying at least two integrated circuits, and where necessary, removing/mitigating the anomaly. The anomaly detection is based on sensing the characteristics of either the current, the voltage, or both the current and voltage of the supply rail connected to the at least two integrated circuits. When an anomaly occurs, the anomaly is detected by one sensing circuit sensing that the characteristics are different from that when the electronic system is functioning normally.

A droop reduction circuit on a die includes a voltage detector circuit to detect voltage droop in a supply voltage received by a first load. The droop reduction circuit further includes a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop. Each of the PSH banks includes at least one power switch having an input terminal, a gate terminal, and an output terminal. The input terminal is to receive a secondary voltage, which is higher than the supply voltage and is also received by a second load on the die. The gate terminal is to receive a drive signal from the driver controller, and the output terminal is to pull up the voltage droop in the supply voltage.

A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.

A semiconductor device includes an internal circuit connected to at least one pad. A first inductor element is connected between the at least one pad and the internal circuit, a second inductor element coupled to the first inductor element and generating an induced voltage due to an overcurrent flowing in the first inductor element. An event detection circuit includes a monitoring element connected to the second inductor element. The monitoring element is configured to generate an event detection signal by sensing changes in properties of the monitoring element caused by at least one of the induced voltages generated in the second inductor element and a current flowing in the second inductor element. The internal circuit supplies an operating voltage to the event detection circuit, and determines whether an event causing the overcurrent has occurred by receiving the event detection signal from the event detection circuit.

An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.

The present technology is to provide a detector capable of detecting an input voltage outside the guaranteed operating voltage range, even if the delay time caused in a logic element by a decrease in power-supply voltage varies due to an external factor. The detector includes a plurality of first detection circuits, a first detection rate calculation unit, a plurality of second detection circuits, a second detection rate calculation unit, and a comparison determination unit. Each of the plurality of first detection circuits detects whether or not an input voltage has a value outside a guaranteed operating range for a normal operation. The first detection rate calculation unit calculates a first detection rate of the detected number of the first detection circuits, and each of the plurality of second detection circuits detects whether or not a predetermined reference voltage is lower than a threshold voltage.

A mode-transition architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes controller includes a controller coupled to a slope compensation circuit, the controller to cause the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck-boost converter is operating in a discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode having a first duty cycle to a second mode and causes the slope compensation circuit to apply a second slope compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation.

A power supply semiconductor integrated circuit includes an output transistor, a control circuit, a first-fault detection circuit, a second-fault detection circuit, a delay circuit, and a latch circuit. The output transistor is connected between a voltage-input terminal to which a DC voltage is input and a voltage-output terminal. The control circuit controls the output transistor. The first-fault detection circuit detects a first fault. The second-fault detection circuit detects a second fault different from the first fault. The delay circuit delays an output of the first-fault detection circuit and an output of the second-fault detection circuit. The latch circuit captures and holds an output of the delay circuit. The delay circuit includes: a constant current source for charging a delay capacitor; a discharge switch for discharging the delay capacitor; and a voltage comparator circuit that compares a charge voltage across the delay capacitor and a predetermined voltage.

A power module according to the present invention switches an operation mode between a control mode where an ON/OFF operation of a switching element having a first electrode, a second electrode, and a third electrode is controlled, and a deterioration determination mode where the deterioration is determined based on information including ΔVgs based on information including a threshold voltage detected before a stress current is supplied to the switching element and a threshold voltage detected after the stress current is supplied to the switching element. According to the power module of the present invention, the deterioration can be determined during an operation time and hence, breaking of the device can be prevented, and operation efficiency of the power module can be increased, and a manufacturing cost of the power module can be lowered.

A circuit includes a voltage comparator with an output, a first input and a second input, the first input being coupled to a first reference voltage terminal. An operational transconductance amplifier has an output coupled to the second input of the voltage comparator, an inverting input coupled to the output of the operational transconductance amplifier, and a non-inverting input coupled to a second reference voltage terminal. A filter capacitor is coupled in series between a power supply terminal and the second input of the voltage comparator.