A drive circuit for an insulated-gate semiconductor element includes a current source which generates a current to be supplied to a gate of the insulated-gate semiconductor element, a current output circuit which controls supply of the current generated by the current source to the gate of the insulated-gate semiconductor element in accordance with a drive signal, an output current control circuit which controls a magnitude of the current generated by the current source in accordance with a control voltage according to an operating temperature of the insulated-gate semiconductor element, and a control voltage detection terminal which is provided in the output current control circuit and enables detection of the control voltage from outside.

A power semiconductor circuit includes: a power semiconductor element having a gate electrode configured to actuate the power semiconductor element, a collector electrode, and an emitter electrode electrically connected to a first emitter terminal; and a temperature sensor having a first measurement point with a measurement terminal and a second measurement point electrically connected to the emitter electrode, so that a voltage which drops over the temperature sensor is measurable between the measurement terminal and the first emitter terminal for the temperature measurement. Corresponding methods for determining a temperature of a power semiconductor element and for determining a sign of a load current in a bridge circuit are also described.

A method for determining failure of a power element for use in an electronic device is provided. The electronic device includes a power element and a detection circuit. The method includes the steps of: obtaining a temperature-calculation model of the power element, and obtaining a parameterized temperature-calculation model of a power-element parameter and a parameterized temperature of the power element; detecting load information and the power-element parameter by the detection circuit; calculating a modeled temperature of the power element according to the load information and the temperature-calculation model, and calculating the parameterized temperature of the power element according to the power-element parameter and the parameterized temperature-calculation model; determining whether an error between the modeled temperature and the parameterized temperature exceeds a permitted range; and determining that the power element has failed in response to the error exceeding the permitted range.

Systems, circuits, and chips for protecting transistors and circuits containing transistors are provided. As an example, a transistor (e.g., an Insulated-Gate Bipolar Transistor (IGBT)) monitoring system is disclosed to include an IGBT desaturation detection circuit that is configured to check and monitor desaturation functionality of the IGBT before startup of the IGBT as well as during operation of the IGBT.

An apparatus for performing the following. The apparatus maintains, in a memory, information on a computational model for thermal behavior of layers of an insulated-gate bipolar transistor, IGBT, module. The apparatus obtains measurements of the dissipated power at the semiconductors and the ambient temperature and determines one or more current values of one or more temperatures of the IGBT module based on a switching delay of the IGBT module. The apparatus calculates a current estimate of a joint state-parameter space of the computational model using a Bayesian filter and the computational model taking as inputs the dissipated power and the ambient temperature. The joint state-parameter space includes the one or more temperatures, one or more thermal loss parameters and one or more wear parameters. The one or more current values of the one or more temperatures are used as observations in the Bayesian filter.

A method for manufacturing a semiconductor device having a trench gate structure is provided. In the method, a first voltage-current characteristic indicating a relation between the main current and the gate voltage under a first temperature is measured to calculate a first threshold voltage. A second voltage-current characteristic indicating a relation between the main current and the gate voltage under a second temperature different from the first temperature is measured to calculate a second threshold voltage. It is determined whether the semiconductor device is a non-defective product or a defective product based on whether a difference between the second threshold voltage and the first threshold voltage is larger than a determination threshold value.

An abnormality detection device includes a first temperature detector, a power consumption calculator, a second temperature detector, and an abnormality determination unit. The first temperature detector detects a detection temperature of an FET that is mounted on a mounting surface of a substrate and that generates heat when energized. The power consumption calculator obtains power consumption of the FET. The second temperature detector detects a detection temperature of a heat sink that is provided on a side opposite to the mounting surface side of the substrate and that dissipates the heat generated in the FET. A controller determines an abnormality in a heat dissipation path P between the FET and the heat sink based on a thermal resistance determined according to the detection temperature detected by the first temperature detector, the detection temperature detected by the second temperature detector, and the power consumption obtained by the power consumption calculator.

A semiconductor device, including: a power semiconductor element having a current output electrode; a wire bonded to the current output electrode; and a degradation detection circuit configured to monitor a temporal change of a voltage value of the wire while a constant current flows through the wire, responsive to satisfaction of a plurality of conditions including that the power semiconductor element is in a turn-off state, and that a temperature of the power semiconductor element is within a predetermined temperature range.

Disclosed is a method for testing and evaluating a short-circuit withstand capability of a press-pack power component. The method includes: building a test platform; obtaining a voltage level, a pressure load, an environment temperature, and a maximum junction temperature fluctuation range of a to-be-tested component in an actual working condition; separately testing short-circuit withstand capabilities of the to-be-tested press-pack power component; monitoring, in real time, changes of a component short-circuit current, a collector-emitter voltage, and a grid-emitter voltage until the to-be-tested press-pack power component fails due to short circuit; correspondingly obtaining a relationship between a voltage and each of a short-circuit critical energy and a critical temperature, a relationship between a pressure and a short-circuit current, and a relationship between a temperature and a short-circuit current; obtaining a relationship between a short-circuit withstand capability of the to-be-tested press-pack power component and each of a voltage, a pressure, and a temperature.

The present invention concerns a method and a device for estimating a level of damage or a lifetime expectation of a power semiconductor module comprising at least one die that is mechanically, thermally, and electrically attached to a substrate, composed of plural layers of different materials. The invention: obtains power losses of the power semiconductor module, obtains the temperature in at least two different locations of the power semiconductor module, estimates a thermal model between the at least two different locations of the power semiconductor module using the determined power losses and the obtained temperatures, determines if a notification indicating the level of damage or the lifetime expectation has to be performed according to the estimated thermal model and a reference thermal model. notifies the level and location of damage or the lifetime expectation if the determining step determines that the notification has to be performed.