An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.

A method evaluates a defect region of a semiconductor substrate based on C-V characteristics of a MOS structure formed on the semiconductor substrate, including determining a relationship between defect region and flat band voltage or fixed charge density by using a semiconductor substrate having a known defect region, under a heat treatment condition and a C-V characteristic evaluating condition identical to conditions for evaluating a defect region of a semiconductor substrate to be evaluated, determining a flat band voltage or a fixed charge density of the semiconductor substrate to be evaluated from C-V characteristics of a MOS structure formed on the semiconductor substrate to be evaluated, and identifying the defect region of the semiconductor substrate to be evaluated based on the relationship between defect region and flat band voltage or fixed charge density previously determined, whereby the defect region of the semiconductor substrate is evaluated.

A method for predicting remaining life of electromigration failure is disclosed. The methods includes: establishing an electromigration life model of a MOS device; acquiring a normal electromigration failure lifetime 1, based on a current density and a first environment temperature under a preset normal operating condition and the electromigration life model; acquiring a current density stress, based on a target prognostic point 2, a second environment temperature and the electromigration life model; inputting the current density stress into a MOS device electromigration failure warning circuit based on a prognostic cell; and if the prognostic circuit of EM failure for a MOS device outputs a high level after a time 3, acquiring a remaining life of electromigration failure corresponding to 2 based on 1, 2 and 3. A device for remaining life prediction for electromigration failure is also disclosed.

A test circuit includes a pull-up device, a pull-down device, a switch circuit and a voltage-setting unit. The pull-up device is used to receive a first control signal and coupled to a first end of the device-under-test. The pull-down device is used to receive a second control signal and coupled to the first end of the device-under-test. The switch unit is controlled by a switch signal, used to receive a testing signal and coupled to a second end of the device-under-test. The voltage-setting unit is controlled by a third control signal, used to pull the second end of the device-under-test to a predetermined voltage.

The present invention provides a measurement system and modeling method for radio frequency MOS device modeling. Electrodes that are correspondingly provided in a slave test structure and a master test structure of the measurement system are different, where a source and a drain of a second MOS device are respectively connected to corresponding test ports, and a gate is independently connected out to facilitate setting a corresponding bias voltage. The modeling method configures an initial value of each parasitic element in a subcircuit model by means of a test result of the measurement system, corrects the initial values of at least some parasitic elements, and finally obtains parasitic parameter values of the parasitic elements.

The present invention relates to a method for characterizing in pulse-mode a III-V semiconductor transistor (2) and an associated test bench (1), wherein an RF pre-pulse is applied to the gate (2a) of the transistor (2) with an power level NRF defined according to a first predetermined law of variation so as to fix the charge state of the traps in the transistor (2), then a first DC pulse and a second DC pulse are applied to the gate (2a) and to the drain (2b) of the transistor (2), respectively, the first DC pulse and the second DC pulse having a first DC level N1 and a second DC level N2, respectively, defined according to a second predetermined law of variation.

A method for manufacturing a display panel including a display unit in which pixels, in rows and columns, include an organic EL element and a drive transistor, includes, performed on the display panel having a line defect which is a pixel column that emits light of luminance not reflecting display gray level signals: displaying, overlappingly, a lighted line, which is a pixel column inputted with uniform display gray level signals, and the line defect by displaying the lighted line on the display unit and scanning the display unit with the lighted line in the row direction; reducing a bright/dark part range in the line defect by uniformly changing the display gray level inputted to the pixel column in the lighted line overlapping with the line defect; and identifying a defective pixel, which is the line defect origin, from the position of the reduced bright/dark part range in the display unit.

In a method for testing an image sensor having (i) regular pixels and test pixels, of which each is interconnected with one of two predefined voltage values, and (ii) a signal processing unit for providing digital signal values for output voltages of the pixels and test pixels, the following steps are performed: receiving digital signal values of the test pixels; and using the signal values of at least one proper or improper subset of the test pixels for testing the image sensor, all test pixels of the subset being interconnected with a first of the two voltage values. Using the test pixels for testing allows testing during ongoing operation, i.e., during reception of regular image signals.

A method evaluates a defect region of a semiconductor substrate based on C-V characteristics of a MOS structure formed on the semiconductor substrate, including determining a relationship between defect region and flat band voltage or fixed charge density by using a semiconductor substrate having a known defect region, under a heat treatment condition and a C-V characteristic evaluating condition identical to conditions for evaluating a defect region of a semiconductor substrate to be evaluated, determining a flat band voltage or a fixed charge density of the semiconductor substrate to be evaluated from C-V characteristics of a MOS structure formed on the semiconductor substrate to be evaluated, and identifying the defect region of the semiconductor substrate to be evaluated based on the relationship between defect region and flat band voltage or fixed charge density previously determined, whereby the defect region of the semiconductor substrate is evaluated.

The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.