The present invention provides a reliable method and arrangement for boundary scan testing and debugging newly manufactured multi-chip modules (MCMs) made to identical design specifications with no Known Good Die therein. Advantageously, a first and a second MCM are temporarily linked in tandem for boundary scan testing through a motherboard and daisy-chaining their internal dice, and interlinking the corresponding boundary scan cells of the identical dice of the first and second MCM to (1) run self-test on individual MCMs and mutual test on the MCMs connected in tandem in order to generate an extended Truth Table that includes responses from an array of combined netlists of the first and second MCMs, and (2) to diagnose mismatched bits in the extended Truth Table using a Boundary Scan Diagnostics software so as to identify defects in the first and second MCMs.

A test method for a semiconductor device includes determining a contact failure between a first semiconductor chip and a second semiconductor chip during assembly of a semiconductor package including the first semiconductor chip and the second semiconductor chip, using a test circuit embedded in the first semiconductor chip, and after the assembly of the semiconductor package, determining whether the semiconductor package is defective by using the test circuit.

The device for testing a motherboard includes a power adapter, a first DC-DC converter, and a microcontroller. The power adapter converts an AC input voltage to a DC supply voltage. The DC-DC converter converts the DC supply voltage to a DC voltage at a channel coupled to the motherboard, and adjusts a voltage level of the DC voltage in response to a control signal. The DC-DC converter is enabled according to an enable signal. The microcontroller is configured to provide the control signal and the enable signal, and to determine whether a power on/off operation of the motherboard is normal. The microcontroller is configured to perform a test procedure on the motherboard to obtain a workable voltage range of the motherboard. The voltage level of the DC voltage in the test procedure is dynamically adjusted within a predetermined range around a nominal voltage value of the DC voltage.

A test access port circuit includes a data input terminal, a reset terminal, a mode selection terminal, at least one test data register set, an auxiliary data register set, an instruction register set, and a controller. The controller is coupled to the mode selection terminal and the instruction register set, and controls the at least one test data register set, the auxiliary data register set, and the instruction register set according to at least mode selection signal received by the mode selection terminal. In a reset terminal input mode, when the controller controls a test data register set of the at least one test data register set to store a first input data bit received by the data input terminal, the auxiliary data register set stores a second input data bit received by the reset terminal.

The disclosure provides an online test data record and offline data conversion analysis system and a method thereof. In the present disclosure, the test process information of the production line testing system performed on the circuit board to be tested is generated into online test result data in a database file format, and the offline analysis system receives the online test data from the production line testing system. The offline analysis system reads the corresponding data in the online test result data according to the designated data in the data designated instruction, and generates the offline test result data in the designated file format of the data designated instruction, and the offline analysis system perform the data analysis for the offline test result according to the analysis instruction.

System and method for autonomous trouble shooting of a unit under test (UUT) having a plurality of replaceable components include: a test station that stores an artificial intelligence (AI) program and a knowledge database (KDB) including acceptable test results for each test point represented by an acceptable test vector, a test probe to test the circuit card assembly; and an operator station to send commands to the test station via the communication network to teach the AI program to capture and store the acceptable test result for each test point of the UUT by the test probe, in the KDB, wherein the AI program commands the test probe to test the UUT, stores the test results in a test result vector, compares the test result vector with the stored acceptable test vector, and displays recommendation as which replaceable component in the UUT to be repaired or replaced.

Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

A circuit board testing device electrically coupled to a measurement gauge tests a circuit board. The circuit board testing device includes a processor configured to configure measurement parameters of the measurement gauge, configure measurement rules for testing the circuit board, confirm a circuit of the circuit board to be tested according to the record of test data, control the measurement gauge to test the circuit of the circuit board to be tested when the measurement gauge is electrically coupled to the circuit of the circuit board to be tested, receive measurement data returned by the measurement gauge, and analyze a faulty region of the circuit board according to the record of test data and the measurement data.

An appliance with automatic sensing of printed circuit board (PCB) trace integrity and associated methods of sensing are provided. The appliance may include a controller operative to control operation of the appliance, a load in operative communication with the controller, and a PCB. The PCB may include a first trace supplying AC power to the load, a second trace supplying a return path for the AC power, a third trace supplying an alternate return path for the AC power, and current sensing circuitry. The current sensing circuitry may be configured to sense leakage current between the first trace and the third trace, with the leakage current being indicative of declining trace integrity of the PCB.

A distributed control system may include a main processing unit, a distributed control module, and a controllable component. The distributed control module may be configured to determine a fault state associated with a control loop using a built-in test module. The built-in test module may be incorporated into the distributed control module. The fault state may include no faults, a communication fault, a sensor operation fault, or a controllable component fault. The distributed control module may be configured to transmit a closed-loop control command from the distributed control module to a controllable component when the fault state comprises no faults, or transmit an augmented control command from the distributed control module to the controllable component when the fault state comprises a communication fault or a sensor operation fault, or transmit a disconnect control command from the distributed control module to the controllable component when the fault state comprises a controllable component fault.