The device for testing a motherboard includes a power adapter, a first DC-DC converter, and a microcontroller. The power adapter converts an AC input voltage to a DC supply voltage. The DC-DC converter converts the DC supply voltage to a DC voltage at a channel coupled to the motherboard, and adjusts a voltage level of the DC voltage in response to a control signal. The DC-DC converter is enabled according to an enable signal. The microcontroller is configured to provide the control signal and the enable signal, and to determine whether a power on/off operation of the motherboard is normal. The microcontroller is configured to perform a test procedure on the motherboard to obtain a workable voltage range of the motherboard. The voltage level of the DC voltage in the test procedure is dynamically adjusted within a predetermined range around a nominal voltage value of the DC voltage.

Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

A circuit board and a method for electrical performance detection thereof, a display panel, a method for fabricating a display panel, and a method for driving the display panel are provided. In the electrical performance detection, the signal output terminal is electrically connected to the detection terminal, and detection is performed on the drive signal by the electrical performance detection circuit to determine whether the circuit board is abnormal, achieving the electrical performance detection of the circuit board. In addition, in a process other than the electrical performance detection, the signal output terminal is disconnected from the detection terminal to avoid affecting a normal operation of the circuit board. The electrical performance detection of the circuit board is realized, a defective circuit board is prevented from flowing into a subsequent fabricating procedure, and waste of assembling resources is avoided.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

A method is provided. The method includes connecting an integrated circuit to a curve tracer, displaying a device signature corresponding to the integrated circuit on a screen of the curve tracer, and comparing the device signature to a reference signature to determine if the integrated circuit is counterfeit.

Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.

Generally discussed herein are systems, devices, and methods for determining if a circuit is acting improperly. A system can include a module to receive proper performance values of a circuit, a module to receive improper performance values of the circuit, a module to compare actual circuit input characteristics (X.sub.a) and actual circuit output characteristics (Y.sub.a) to X, Y, D, and Z to determine if the circuit is more likely operating properly or more likely operating improperly, and an alert module to, in response to determining the circuit is operating improperly, provide an alert to personnel indicating that the circuit is operating improperly or providing one or more signals to the circuit that cause the circuit to alter its current operation.

A dual gate array substrate is disclosed. In two vertically adjacent pixel pairs, two pixel units in each of the pixel pairs are connected to the same data line of the two adjacent data lines respectively, and two adjacent pixel units in the two pixel pairs in an extending direction of the data line are connected to different data lines in the two adjacent data lines respectively; in two adjacent pixel pairs in an extending direction of any set of the dual gate lines, a data line connected to two pixel units in one pixel pair is different from but adjacent to a data line connected to two pixel units in the other pixel pair; and two adjacent pixel units in the extending direction of the data line are connected to their respective adjacent gate lines transmitting different scan signals respectively.

A method is provided. The method includes connecting an integrated circuit to a curve tracer, displaying a device signature corresponding to the integrated circuit on a screen of the curve tracer, and comparing the device signature to a reference signature to determine if the integrated circuit is counterfeit.

Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.