A burn-in chamber is provided, configured to provide the required temperature for a device under test (DUT), including a side wall, a guiding plate, an air flow plate, a partition assembly, and a fan. The air flow plate has a ventilation structure, and the guiding plate is located between the side wall and the air flow plate. The partition assembly is disposed on both sides of the air flow plate. The partition assembly and the air flow plate together form an accommodating space for accommodating the DUT. The partition assembly forms a return channel with respect to the other side of the accommodating space with the side wall. When the fan is active, air from the accommodating space passes through the air flow plate and is guided to the return channel via the guiding plate, and air is returned to the accommodating space through the return channel.

A device for testing performance of main boards of electronic devices includes a housing, two bases, a control device, a humidifier, a heating device, and a refrigerating device. A cavity in the housing comprises separated first and second portions. The heating device is interconnected with the first portion to create a predefined high temperature environment and the refrigerating device is interconnected with the second portion to create a predefined low temperature environment. The humidifier is interconnected with the first portion and the second portion, and configured to create predefined degrees of humidity respectively in the first portion and the second portion. The bases are inside the first portion and the second portion, and electrically connected to the control device.

A multi-die health monitoring device: sets, at a given current provided to the load by the group of dies, one of the dies in a non-conducting state (NCS), obtains, when the die is in the NCS, a signal that is representative of the temperature of the die and determines the temperature of the die, obtains, when the die is in the NCS, a signal that is representative of an on-state voltage (OSV) of the die and determines the OSV of the die, retrieves in a table stored in a memory of the multi-die health monitoring device, an OSV that corresponds to the given current and the determined temperature of the die, notifies that the multi-die power module has to be replaced, if the difference between the determined OSV of the die and the retrieved OSV is equal or upper than a predetermined value.

Method for estimating degradation of a wire-bonded power semiconductor module (1) comprising: a) obtaining an indicator of degradation (Degr.sub.est_t-1); b) estimating (11) an estimated indicator of degradation (Degr.sub.est_t) by a temporal degradation model; c) obtaining (3) a set of on-line measure (X.sub.on_meas_t); then, d1) converting (13) the on-line measure (X.sub.on_meas_t) into a deducted indicator of degradation (Degr.sub.meas_t) by an electrical equivalence model, and e1) computing (15) a deviation between estimated and deducted indicator of degradation (Degr.sub.est_t; Degr.sub.meas_t); and/or d2) converting (13) the estimated indicator of degradation (Degr.sub.est_1) into a set of on-line estimation (X.sub.on_est_t), and e2) computing (15) a deviation between set of on-line measure and estimation (X.sub.on_ meas_t; X.sub.on_est_t); and f) correcting (17) the estimated indicator of degradation (Degr.sub.est_t) into a corrected estimated indicator of degradation (Degr.sub.corr_t) in function of the computed deviation.

In a power supply system, a high-side (HS) insulated-gate bipolar transistor (IGBT) has a first collector, a first gate, and a first emitter. A low-side (LS) IGBT has a second collector coupled to the first emitter, a second gate, and a second emitter. A gate drive circuit is coupled to the first gate of the HS IGBT and the second gate of the LS IGBT. A control circuit is coupled to the gate drive circuit. The control circuit is configured to control the gate drive circuit for biasing the HS IGBT to a HS saturation, and determine a HS degradation of the HS IGBT based on a HS digitized gate voltage of the HS IGBT in the HS saturation.

A failure prediction device is provided for predicting, using a structure having a high degree of design freedom, failure at a soldered joint due to vibration stress, and a circuit board using the same. The failure prediction device is disposed on a substrate having a mounting component that is fixed thereon through a solder joint. The failure prediction device is provided with a load amplifying portion that includes a pair of support leg portions each having one end to be fixed to the substrate or the mounting component, and a sacrificial fracture portion that is supported by the other ends of the pair of support leg portions, wherein the load amplifying portion transmits, to the sacrificial fracture portion via the pair of support leg portions, vibration that is applied to the substrate.

Techniques for environmental contaminant monitoring are disclosed. In some embodiments, a contaminant detection system electronically instigates a test circuit that shares an environment with another circuit to induce an electrical anomaly in the test circuit when environmental contamination is present. While electronically instigating the first circuit, the contaminant detection system monitors for an electrical anomaly indicative of the environmental contamination. Responsive to detecting an electrical anomaly in the test circuit that is indicative of environmental contamination, the contaminant detection system generates an alert that indicates that the second circuit has likely been exposed to the environmental contamination. The contaminant detection system may provide early warning of potentially caustic environments before creep corrosion or similar phenomena manifest in expensive hardware resources. Thus, hardware outages may be mitigated or avoided.

Techniques are described for systematically and efficiently converting or otherwise accelerating latent defects in semiconductor devices into gross defects by applying appropriate defect acceleration stimulus to the semiconductor devices. Techniques are also described for evaluating test patterns to determine their effectiveness in accelerating the transition of latent defects to gross defects. This evaluation effectively allows various stress patterns to be graded or ranked, so that an optimal or high-confidence one can be selected. Such grading of possible stress patterns increases the probability that a given latent defect will escalate or otherwise manifest.

A method estimates a level of damage or a lifetime expectation of a power semiconductor module having at least one die that is mechanically and electrically attached to a ceramic substrate. The ceramic substrate has piezoelectric properties and the method includes: controlling the at least one power die, the control of the at least one power die generating changes in the electrical potential across the ceramic substrate; obtaining information representative of a mechanical deformation of the ceramic substrate; determining if a notification indicating the level of damage or the lifetime expectation has to be performed according to the obtained information and reference information; and notifying the level of damage or the lifetime expectation if the determining step determines that the notification has to be performed.

An isolated insulated gate bipolar transistor (IGBT) gate driver is provided which integrates circuits, in-module, to support the measurements of threshold voltage, and collector-emitter saturation voltage of IGBTs. The measured gate threshold and collector-emitter saturation voltage can be used as precursors for state of health predictions for IGBTs. During the measurements, IGBTs are biased under specific conditions chosen to quickly elicit collector-emitter saturation and gate threshold information. Integrated analog-to-digital converter (ADC) circuits are used to convert measured analog signals to a digital format. The digitalized signals are transferred to a micro controller unit (MCU) for further processing through serial peripheral interface (SPI) circuits.