Modulation testing separately enables slices of an analog varactor array of an LC oscillator. For each enabled slice, a reference voltage supplying a resistor ladder is set to a plurality of different reference voltage values. Resistor ladder voltages generated for the different reference voltage values are supplied to the enabled slice and a control voltage coupled to the enabled slice is swept for each of the reference voltage values. Respective frequencies of an oscillator signal coupled to an output of the LC oscillator are measured for each enabled slice for each combination of the reference voltage values and the control voltage values. The linearity of LC oscillator gain is determined for each of the reference voltage values for each slice based on the respective frequencies and the control voltage values. Passing/failing the modulation testing is based on the linearity of the LC oscillator gain.

A measurement system includes a narrowband receiver configured to receive an input signal with an initial bandwidth. The narrowband receiver includes at least one local oscillator configured to provide a local oscillator signal having a center frequency and at least one signal mixer configured to mix the input signal and the local oscillator signal to obtain a mixed signal including image portions. The mixed signal has a respective center frequency in view of the local oscillator signal mixed therein. The narrowband receiver is configured to process two or more mixed signals, thereby obtaining two or more captured signals for different center frequencies of the local oscillator signal. The two or more captured signals have a limited bandwidth compared to the initial bandwidth. The narrowband receiver is configured to combine the two or more captured signals in order to obtain a processed signal without image portions.

A BIST system and method for a crystal oscillator amplifier including current mirror circuitry, an ADC, a DAC, and test control circuitry. The amplifier includes a current source, a base transistor and a feedback resistor. The ADC converts a self-bias voltage on an input node into a digital bias code during a normal mode when the current source is coupled to the base transistor. During phases of a test mode, the base transistor is coupled instead to the mirror circuitry, which mirrors current through the base transistor into a test resistor. The digital bias code is converted into upper and lower digital bias codes using a delta value, which are converted by the DAC into corresponding bias voltages driven onto the input node during respective phases of the test mode. The ADC converts corresponding test voltages on the test resistor into test codes used to estimate the amplifier transconductance.

An integrated circuit includes a multiplexer circuit coupled to receive a first clock signal and a second clock signal and coupled to provide an output clock signal to a channel. A protection circuit is coupled to receive a feedback signal from the channel. The protection circuit causes the multiplexer circuit to provide oscillations in the second clock signal to the output clock signal in response to the feedback signal indicating that the channel is idle to cause the channel to be in a protection mode that reduces degradation from bias temperature instability. The protection circuit causes the multiplexer circuit to provide oscillations in the first clock signal to the output clock signal in response to the feedback signal indicating that the channel is active.