A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period. Accordingly, a characteristic of the electrical quantity at each of the respective test output conductors over the duration of the longest period of the unique periods is indicative of any disturbance between the discrete output signals associated with the test output conductor and all of the other discrete output signals.

A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

A display device according to a present disclosure comprises: a display region; a frame region disposed around the display region; a plurality of first wirings extending in a first direction in the display region; a first drive circuit electrically connected to one end of each of the plurality of first wirings; a first inspection wiring electrically connected to another end of each of the plurality of first wirings through each of a plurality of inspection thin film transistors; a second inspection wiring connected to a gate electrode of each of the plurality of inspection thin film transistors; an inspection drive circuit electrically connected to the second inspection wiring; and an inspection circuit electrically connected to the first inspection wiring, wherein at least a part of the second inspection wiring extends in the first direction in the display region.

A system includes a signal generator, configured to pass a generated signal, which has two different generated frequencies, through a circuit including an intrabody electrode. The system further includes a processor, configured to identify, while the generated signal is passed through the circuit, a derived frequency, which is derived from the generated frequencies, on the circuit, and to generate, in response to identifying the derived frequency, an output indicating a flaw in the electrode. Other embodiments are also described.

In one embodiment, an apparatus includes a bi-directional coupler for coupling an upstream signal and a downstream signal to a termination load. A test point detection mechanism is configured to detect when a test point device is inserted in a test point connector. The test point device is configured to perform a test of the upstream signal or the downstream signal. A switch is configured to switch from being coupled to the termination load to being coupled to the test point device when the test point device is detected as being inserted in the test point connector. The switch is configured to switch from being coupled to being coupled to the test point device to the termination load when the test point device is detected as being removed from being inserted in the test point connector.

There is provided an aircraft engine printed circuit board assembly generally having a functional circuit contributing to the operation of an aircraft engine. The functional circuit has a first substrate portion, a first electronic component supported by the first substrate portion, and a first electrical conductor supported by the first substrate portion and leading to the first electronic component. The aircraft engine printed circuit board assembly generally has a monitoring circuit having a second substrate portion, a second electronic component supported by the second substrate portion, a second electrical conductor supported by the second substrate portion and leading to the second electronic component, the second electrical conductor having a shorter life expectancy than the first electrical conductor, and a detector monitoring an indicator of operativeness of the second electrical conductor, in which the first electrical conductor and the second electrical conductor are both exposed to the same environment.

In one embodiment, an apparatus includes a bi-directional coupler for coupling an upstream signal and a downstream signal to a termination load. A test point detection mechanism is configured to detect when a test point device is inserted in a test point connector. The test point device is configured to perform a test of the upstream signal or the downstream signal. A switch is configured to switch from being coupled to the termination load to being coupled to the test point device when the test point device is detected as being inserted in the test point connector. The switch is configured to switch from being coupled to being coupled to the test point device to the termination load when the test point device is detected as being removed from being inserted in the test point connector.

Disclosed are a power-loss delay circuit and a detection control circuit thereof. The power-loss delay circuit and the corresponding detection control circuit are added onto a flyback circuit, such that when a product is working normally, an energy storage capacitor C3 is charged, and when an input power supply of the product is cut off, the detection control circuit detects that an input voltage of the product drops to a set value and triggers the control circuit to drive a switch transistor Q1 to be turned on, so that the energy of an energy storage capacitor C1 is released, thereby keeping the product working continuously for a period of time. The power-loss delay circuit and the detection control circuit thereof have no effect on the normal working state of the product. When the input power is cut off, capacitance stored in an external capacitor is introduced in time to keep the product working continuously. In the present invention, extended power-loss holding time, small inrush current, high efficiency, simple circuit structure, and high reliability are achieved, and a power-loss delay protection threshold may be automatically adjusted according to change in under-voltage points, making systematic application of modular power supply more convenient.

A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.