A method includes providing a detector disposed above a semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector; rotating the stage; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.

A manufacturing method of an electronic device and an electronic device are provided. The manufacturing method includes the following steps: providing a substrate; forming a plurality of signal lines and a testing circuit on the substrate, wherein the testing circuit includes a plurality of output channels electrically connected to at least a portion of the plurality of signal lines; performing a testing process; and optionally isolating the testing circuit from the at least a portion of the plurality of signal lines. The testing process includes: providing a signal; processing a plurality of testing signals by processing the signal via the testing circuit; and transmitting the plurality of testing signals to the at least a portion of the plurality of signal lines via the plurality of output channels. The plurality of output channels are less than the plurality of signal lines in quantity.

A system and method for an LCDI power cord and associated circuits is provided. The system and method include energizing shielded neutral wires and shielded line wires and monitoring the energized shields for surges, e.g., arcing, detected by a Leakage Current Detection Circuit (LCDC) and/or voltage drops, e.g., shield breaks, detected by a Shield Integrity Circuit (SIC).

A semiconductor integrated circuit includes: a main circuit; a non-volatile memory; and a self-diagnosis circuit configured to execute, when the semiconductor integrated circuit is to be powered off, self-diagnosis processing in which the main circuit is diagnosed and a diagnosis execution record indicating whether the diagnosis is completed and a diagnosis result indicating a result of the diagnosis are stored in the non-volatile memory. The self-diagnosis circuit is configured to: determine, when the semiconductor integrated circuit is powered on, whether there is a failure in the main circuit by reading the diagnosis execution record and the diagnosis result out of the non-volatile memory; and shift a state of the main circuit to a safe state when determining that there is a failure in the main circuit, and instruct the main circuit to start normal operation when determining that there is no failure in the main circuit.

A system and method for an LCDI power cord and associated circuits is provided. The system and method include energizing shielded neutral wires and shielded line wires and monitoring the energized shields for surges, e.g., arcing, detected by a Leakage Current Detection Circuit (LCDC) and/or voltage drops, e.g., shield breaks, detected by a Shield Integrity Circuit (SIC).

A method, system and computer readable medium for determination of distance to an electrical fault within a device. A signal generator excites the device with an electrical input signal. The device comprises an open circuited electrical transmission line. A frequency domain analyzer analyzes part of the signal reflected from the device for determination of the locations of resonant frequency of the signal within the device. A computer calculates the distance to the fault within the device, based on the resonant frequency. The distance to the fault is one quarter wavelength distance into the device at the resonant frequency. A frequency sweeper sweeps the frequency of the input signal and repeated calculation of the distance to the fault made at a plurality of resonant frequencies during the frequency sweep confirms the distance to the fault by convergence of the result of the repeated calculations to substantially the same location.

A method includes loading the semiconductor structure on a stage; providing a detector disposed above the semiconductor structure and the stage; applying a voltage to the semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector; rotating the stage and recording a rotation of the stage after identifying the portion of the semiconductor structure; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.

A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

An fault detection circuit includes a first comparison unit, a second comparison unit, an impedance unit and a digital control unit, the first comparison unit is configured to output a first judgment signal based on the voltage across a sampling resistor; the second comparison unit is configured to output a second judgment signal based on the voltage across the impedance unit, or the second comparison unit is configured to output a second judgment signal based on the voltage across the circuit in which the sampling resistor is connected in series with the impedance unit, and the digital control unit is configured to determine the working state of the sampling resistor based on the first judgment signal and the second judgment signal. Through the above method, the accuracy of overcurrent protection can be improved under the condition where the sampling resistor fails.

An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.