G01R31/2846

METHOD FOR PREDICTING A REMAINING FAILURE OR LIFETIME OF AN ELECTRICAL COMPONENT OF AN ELECTRICAL CIRCUIT

The present invention provides a method for predicting a remaining lifetime of an electrical component of an electrical circuit, the electrical circuit being part of a building management device. The method comprises: estimating (S1) two or more estimated temperatures of the electrical component by using a trained machine learning model of the electrical component that is trained based on training data. Further, the method comprises: generating (S2) a temporal course of temperature of the electrical component based on the two or more estimated temperatures; and computing (S3), based on the temporal course of temperature of the electrical component, an indicator for the remaining lifetime of the electrical component. The present invention also provides a method for predicting a remaining lifetime of an electrical circuit being part of a building management device.

Multiple circuit board tester

The present invention is directed to a system for testing printed circuit boards. The system is configured to test the simultaneously test a multiplicity of printed circuit boards. The system examines the electrical characteristics of a printed circuit board and is operable to identify if a printed circuit board meets a desired characteristic.

Method for recognizing partial discharges emitted inside or outside an electrical apparatus

A method of recognizing partial discharges emitted inside or outside electrical equipment after at least one partial discharge activity has been detected Partial discharge patterns are recorded beforehand in a data base, each pattern being associated with the type of fault that generated it. A new partial discharge (Pd) pattern is acquired. The new partial discharge pattern is compared with discharge patterns that are already recorded in the data base The matching fault in the equipment is obtained by deduction, and the result is recorded in the data base.

CIRCUIT WORKING STATE TESTING METHOD AND TESTING DEVICE
20190228691 · 2019-07-25 ·

There are provided a detection method and detection apparatus of an operating state of a circuit. The method includes: forming a neural network that acquires a state category of a circuit to be detected; measuring electrical characteristic parameters of at least one node in the circuit to be detected; inputting the measured electrical characteristic parameters of at least one node to the neural network, and obtaining the state category of the circuit to be detected through the neural network.

RECORDING MEDIUM RECORDING VIA LIFETIME CALCULATION PROGRAM, VIA LIFETIME CALCULATION METHOD, AND INFORMATION PROCESSING DEVICE

A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, ={(LtE)/(DT)}m, where is the amount of distortion, L is a length of the via, is a thermal expansion coefficient of a base material, t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression N.sup.x=C/.

Automated analog fault injection

Systems and methods are provided for an automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.

Closed loop simulation of a computer model of a physical system and an actual real-time hardware component of the physical system

A method and system for performing closed loop simulation of a computer model of a physical system and a hardware component of the physical system is provided. An input waveform for the component from the simulated model of the physical system using an initial waveform as a response waveform of the component is generated at a simulation processor. The input waveform is sent from the simulation processor through a network to a real-time playback and record device (RTPR). The RTPR plays back the input waveform in real time to the component and receives a response waveform of the component and provides the response waveform to the simulation processor. Waveform relaxation (WR) converging methods are utilized at the simulation processor to enable convergence of the generated waveforms affected by hardware induced distortions. A WR method with the generated waveforms are performed to provide a closed loop response of the component.

PARTIAL DISCHARGE DETERMINATION APPARATUS AND PARTIAL DISCHARGE DETERMINATION METHOD
20240183894 · 2024-06-06 ·

A partial discharge determination method executed in a partial discharge determination apparatus that determines whether or not partial discharge has occurred in a power transmission facility includes: acquiring measurement data representing a charge amount and a phase of each partial discharge occurring in the power transmission facility; removing or reducing noise included in the measurement data based on statistical information; generating ?-q-n data representing a charge amount, a phase, and the number of pulses of each of the partial discharge and the noise included in the measurement data from the measurement data from which the noise has been removed or reduced; and determining whether or not at least the partial discharge has occurred by using a learning model generated by performing machine learning using the ?-q-n data of the partial discharge and the noise based on the ?-q-n data generated by a ?-q-n data generation unit.

SUBSTRATE INSPECTION APPARATUS
20190107557 · 2019-04-11 ·

There is provided a substrate inspection apparatus capable of inspecting the electrical characteristics of a packaged semiconductor device in a mounting environment. A prober includes a test box, a probe card and a package inspection card. A packaged device is attached to the package inspection card. A test board of the test box and a card board of the package inspection card reproduce the mounting environment in which a wafer-level system-level test is performed.

AUTOMATED ANALOG FAULT INJECTION

Systems and methods are provided for automated analog fault injection including creating a list of fault models for injection to an analog circuit, adding a first fault placeholder to the analog circuit, running fault simulations by replacing the first fault placeholder with a first fault model from the list of fault models, and determining whether the first fault model is detected.