Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require I.sub.DD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.

An apparatus for testing a transducer module includes a test signal generator coupled to a common-mode terminal common to a plurality of transducers, and a signal processing circuit configured to receive output signal from each of said transducers and to produce an output signal. If the transducers are well matched to one another, the output signal will have little or no output amplitude. If there is a mismatch between the transducers, however, the output signal will have an amplitude proportional to the mismatch. The amplitude of the output signal may be compared to a predetermined threshold in order to produce a mismatch output signal indicating the existence of, and/or the degree of, mismatch between the transducers.

Examples disclosed herein relate to a on-chip or built-in self-test (BIST) module for an RFIC including means to up-convert a signal from a test frequency to RF at an input to the RFIC and down-convert and output signal.

A sensor system included in an integrated circuit includes multiple sensor circuits and a control circuit. Using characterization data, a model may be generated that defines a relationship between measurable parameters of the integrated circuit and an operating characteristic of the integrated circuit. The control circuit can combine, using a function included in the model, data from the multiple sensor circuits to determine a value of the operating characteristic that is more accurate than a sensor circuit configured to measure a single parameter of the integrated circuit that varies with the operating characteristic.

Methods and systems for automated testing of extremely-high frequency devices are disclosed. A device under test (DUT) is set in a simultaneous transmit and receive mode. The DUT receives a lower frequency radio frequency (RF) signal from a test unit and up-converts the lower frequency RF signal to a higher frequency RF signal. The DUT transmits the higher frequency RF signal using a first antenna, and receives the higher frequency RF signal using a second antenna. The DUT down-converts the received higher frequency RF signal to a received test RF signal and provides the received test RF signal to the test unit for comparing measurements derived from the received test signal to a design specification for the DUT.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

A method of detecting a failure of an antiparallel thyristor, wherein the antiparallel thyristor includes a first thyristor and a second thyristor connected in parallel and in opposite directions, and is configured to control power supplied from an alternating current power supply to a load, the method including: detecting, as a first detection value, a voltage or a current supplied to the load when ceasing an output command for the second thyristor and issuing an output command for the first thyristor; detecting, as a second detection value, the voltage or the current supplied to the load when ceasing the output command for the first thyristor and issuing the output command for the second thyristor; and determining the failure of the antiparallel thyristor based on a difference between the first detection value and the second detection value.

A low voltage differential signaling (LVDS) receiver includes a receiver circuit including first and second inputs coupled to first and second conductive pads, respectively, and an output coupled to an input of a digital controller, and a dummy transmitter circuit including a first input coupled to receive a common mode voltage (VCM) tune signal, a second input coupled to a loopback input signal, a third input coupled to a loopback enable signal, a first output coupled to the first input of the receiver circuit, and a second output coupled to the second input of the receiver circuit. When a test mode of operation is enabled, the digital controller asserts the loopback enable signal, and the dummy transmitter circuit generates a pair of test differential signals based on the VCM tune signal, wherein the VCM tune signal varies to test the LVDS receiver over a range of common mode voltages.

A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

In accordance with at least one aspect of this disclosure, a failure detection system for an integrated circuit component includes an integrated circuit component configured to connect to a circuit board, a first sensor operatively connected to sense and output a signal indicative of an actual current output of the component in a first state, and a second sensor operatively connected to sense and output a signal indicative of an actual condition of the component in the first state. A logic module can be configured to output a component failed state signal based at least in part on the signal indicative of the actual current output of the component in the first state and the signal indicative of the actual condition of the component in the first state.