Embodiments of the present disclosure relate to solutions for introducing personalization data in nonvolatile memories of a plurality of integrated circuits, comprising writing in the nonvolatile memory of a given integrated circuit a static data image, corresponding to an invariant part of nonvolatile memory common to the plurality of integrated circuits, and a personalization data image representing data specific to the given integrated circuit.

A method for screening a semiconductor device for production of excessive random telegraph sequence (RTS) noise includes measuring noise of the semiconductor device at a first temperature, changing the temperature of the semiconductor device to a second temperature different from the first temperature, measuring noise of the semiconductor device at the second temperature, extracting a characteristic of the measured noise at the first and second temperatures (e.g., standard deviation, HMM output, frequency domain spectrum of time domain noise measurement), making a comparison of the extracted first and second noise characteristics, and making a determination whether the semiconductor device produces excessive RTS noise based on whether the comparison is above a predetermined threshold. Two different bias conditions of the device may be employed rather than, or in addition to, the two different temperatures.

A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.

A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

Methods and systems for automated testing of extremely-high frequency devices are disclosed. A device under test (DUT) is set in a simultaneous transmit and receive mode. The DUT receives a lower frequency radio frequency (RF) signal from a test unit and up-converts the lower frequency RF signal to a higher frequency RF signal. The DUT transmits the higher frequency RF signal using a first antenna, and receives the higher frequency RF signal using a second antenna. The DUT down-converts the received higher frequency RF signal to a received test RF signal and provides the received test RF signal to the test unit for comparing measurements derived from the received test signal to a design specification for the DUT.

A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards. Also disclosed is a semiconductor component burn-in test equipment using at least one semiconductor component burn-in test module.

In some examples, a circuit comprises a function unit configured to perform a circuit function, and one or more in situ monitors configured to measure internal data associated with the circuit. The circuit may further comprise a memory configured to store one or more limit values associated with the one or more in situ monitors, and a lifetime model unit configured to determine whether the circuit has reached an end-of-life threshold based on the measured internal data from the one or more in situ monitors and the limit values.

In some examples, this disclosure describes a method of operating a circuit. The method may comprise performing a circuit function under normal operating conditions, wherein performing the circuit function under the normal operating conditions includes performing at least a portion of the circuit functions via a characteristic circuit, performing at least the portion of the circuit function under enhanced stress conditions via a characteristic circuit replica, and predicting a potential future problem with the circuit function under the normal conditions based on an evaluation of operation of the characteristic circuit relative to operation of the characteristic circuit replica.

In some examples, a method of operating a circuit may comprise performing a circuit function under normal conditions, performing the circuit function under aggravated conditions, predicting a potential future problem with the circuit function under the normal conditions based on an output of the circuit function under the aggravated conditions, and outputting a predictive alert based on predicting the potential future problem.

A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.