A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.

A first relational expression for a temperature of a semiconductor device and forward voltage of a temperature measurement diode is obtained in advance. A second relational expression is obtained in advance for ON voltage of the semiconductor device and an amount of temperature change from a first time point before ON of the semiconductor device until a second time point after OFF of the semiconductor device. An amount of forward voltage change of the temperature measurement diode from the first time point until the second time point is obtained. Next, the amount of temperature change from the first time point until the time second point is calculated using the first relational expression and the amount of forward voltage change. An ON voltage of the MOS gate semiconductor device after correction for the calculated amount of temperature change is obtained using the second relational expression.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.

Techniques regarding autonomous identification of aged circuits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an identification component, operatively coupled to the processor, that can identify an aged circuit by analyzing a current-voltage characteristic curve for a distortion in a sub-threshold quiescent current signature of the aged circuit.

Techniques regarding autonomous identification of aged circuits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an identification component, operatively coupled to the processor, that can identify an aged circuit by analyzing a current-voltage characteristic curve for a distortion in a sub-threshold quiescent current signature of the aged circuit.

A soft error inspection method for a semiconductor device includes: irradiating and scanning the semiconductor device with a laser beam or an electron beam; and measuring and storing a time of bit inversion for each of areas irradiated with the laser beam or the electron beam of the semiconductor device.

The present invention relates to a system and method for the simultaneous testing of radiation, environmental and electrical reliability of multiple semiconductor devices. The system provides a simultaneous simulation of the space environment in which a device under test (DUT) is expected to operate under thereby providing an accurate test environment. One or more DUTs are simultaneously subject to each of a radiating dose, electrical bias and varying temperature. Additionally, each of the above may be varied over a range of values to provide test data under multiple testing conditions. Finally, a method for operating the system is provided which ensures reliable and high fidelity data from the system. The system comprises seven (7) interconnected subsystems, an electrical environmental subsystem, a radiation subsystem, an environmental control system, a radiation source control system, a temperature monitoring subsystem, an electrical stimulation and data acquisition subsystem and a data processing and analysis subsystem.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.