Patent classifications
G01R31/2887
CRYOGENIC WAFER TEST SYSTEM
One example includes a cryogenic wafer test system. The system includes a first chamber that is cooled to a cryogenic temperature and a wafer chuck confined within the first chamber. The wafer chuck can be configured to accommodate a wafer device-under-test (DUT) comprising a plurality of superconducting die. The system also includes at least one wafer prober configured to implement a test on a superconducting die of the plurality of superconducting die via a plurality of electrical probe contacts. The system further includes a wafer chuck actuator system confined within a second chamber. The wafer chuck actuator system can be configured to provide at least one of translational and rotational motion of the wafer chuck to facilitate alignment and contact of a plurality of electrical contacts of the superconducting die to the respective plurality of electrical probe contacts of the at least one wafer prober.
JIG
A jig (30) includes a first block portion (100) at which a probe head (300) is installed, and a first suction port (112) formed on the first block portion (100). Air present on a side where one end of a probe (330) provided in the probe head (300) is located is sucked from the first suction port (112).
APPARATUS AND METHOD FOR TESTING ALL TEST CIRCUITS ON A WAFER FROM A SINGLE TEST SITE
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.
PAD STRUCTURE AND TESTKEY STRUCTURE AND TESTING METHOD FOR SEMICONDUCTOR DEVICE
The present disclosure provides a pad structure and a testkey structure and a testing method for a semiconductor device. The pad structure includes: an insulating dielectric layer formed on a substrate; a metal interconnection structure formed in the insulating dielectric layer, the metal interconnection structure comprising a first section and a second section, which are insulated from each other; and a pad formed on the top of the insulating dielectric layer so as to be exposed therefrom at least at its top surface, electrically connected to the first section, and insulated from the second section. With this disclosure, reduced capture of plasma is achievable, mitigating adverse impact of plasma on the semiconductor device.
Docking device and method for coupling second devices for interface units, disposition system and docking element
A docking device for coupling a test device (31) or storage device (30) (first device) for interface units (33) for testing electronic components to at least one handling unit (32) for handling and/or transporting interface units (33) (second device), has a first docking element (1) and a second docking element (2), the first docking element (1) being movable relative to the second docking element (2) and being fixable in an end position. A sensor arrangement is provided for detecting the end position of the first docking element (1) relative to the second docking element (2) on the side of the first device and/or on the side of the second device.
ALIGNMENT METHOD AND INSPECTION APPARATUS
There is provided an alignment method of a probe card including a plurality of probe groups provided corresponding to a plurality of chips, comprising: a first mode for calculating a gradient and a center of a probe group based on position information of two or more probes included in the probe group for each of the plurality of chips and calculating a gradient and a center of the probe card based on the calculated grandients and the calculated centers of the plurality of probe groups.
Semiconductor wafer testing system and related method for improving external magnetic field wafer testing
In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
PROBE AND PROBE CARD DEVICE
The present disclosure provides a probe and a probe card device. The probe card device includes a first plate and a plurality of probes. The probes are arranged through the first plate, and include a first probe and a second probe. The first probe has a first body and an end portion of the first body. The end portion of the first body has a first recess and a first protrusion. The second probe has a second body and an end portion of the second body. The end portion of the second body has a second recess and a second protrusion. The second protrusion extends into the first recess.
Apparatuses and methods for mitigating sticking of units-under-test
Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.
Inspection Device and Method
A stage, electric probes, an optical probe, an electric measurement device, an optical measurement device, and a first positioning mechanism are provided. The stage includes a second positioning mechanism that changes relative positional relationship between the electric probes and an electric connection portion of each of the optical elements. The electric probes electrically connect the electric measurement device and each of the optical elements. The optical probe optically connects the optical measurement device and each of the optical elements. The first positioning mechanism changes relative positional relationship between the optical probe and an optical connection portion of each of the optical elements.