A direct-current power supply applies a DC voltage to test semiconductor devices. A current detection unit detects a leakage current of a test circuit in which test semiconductor devices are included. A measuring instrument records a pulse waveform of the leakage current. An analyzer analyzes reliability of test semiconductor devices included in the test circuit based on the recorded pulse waveform.

Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.

A testing system includes a Device Under Test (DUT) interface structured to couple to one or more DUTs and a device characterization circuit structured to be controlled to perform static testing and dynamic testing of the one or more DUTs. The device characterization circuit includes a drain amplifier coupled to a drain of the one or more DUTs that is structured to measure drain leakage current. Methods of measuring drain current in a device that performs both static and dynamic testing are also described.

In an embodiment, a power switch controller for driving a back-to-back power switch includes: an amplifier having a supply terminal configured to receive a supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switch, a first input configured to be coupled a source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier.

One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current. The method further includes calculating the quiescent current based on the switching current.

A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

In an embodiment, a power switch controller for driving a back-to-back power switch includes: an amplifier having a supply terminal configured to receive a supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switch, a first input configured to be coupled a source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier.

The present invention provides a semiconductor integrated circuit for detecting leakage current to determine whether an electric leakage occurs in an electric line based on an induced voltage input from a leakage current detection unit 20 installed in the electric line, and an earth, leakage circuit breaker having the semiconductor integrated circuit. A semiconductor integrated circuit 100 for detecting leakage current includes: a signal amplification unit 110 configured to amplify the induced voltage; an interruption determination unit 130 configured to compare an output voltage output from the signal amplification unit with a preset reference voltage, and output an interruption signal for interrupting a power supply to the electric line; a flare current stabilization (FCS) circuit 150 for a signal amplification unit connected to the signal amplification unit; and a flare current stabilization (FCS) circuit 170 for an interruption determination unit connected to the interruption determination unit.

A performance testing method for determining a performance of a device under test having non-linear characteristics is disclosed. The performance testing method comprises the following steps: generating a hard clipper model of said device under test; generating a test signal having predefined properties; forwarding said test signal to the device under test, wherein the device under test generates an output signal based on said test signal; feeding said hard clipper model with said test signal, thereby generating a model output signal; and comparing said output signal to said model output signal in order to determine the performance of the device under test.

Moreover, a measurement system for determining a performance of a device under test having non-linear characteristics is disclosed.