Provided is a semiconductor inspection device capable of high-speed response analysis as defect analysis of a fine-structured device constituting an LSI. Therefore, the semiconductor inspection device includes a vacuum chamber 3, a sample table 4 which is disposed in the vacuum chamber and on which a sample 6 is placed, an electron optical system 1 disposed such that an electron beam is emitted from above the sample, a plurality of probe units 24 connected to external devices 11 and 12 disposed outside the vacuum chamber via a coaxial cable 10, and an electrode 5 provided on or in the vicinity of the sample table. The probe unit 24 includes a measurement probe 8 configured to come into contact with the sample, a GND terminal 9 configured to come into contact with the electrode 5, and a probe holder 7 configured to hold the measurement probe and the GND terminal, connect a signal line of the coaxial cable to the measurement probe, and connect a GND line of the coaxial cable to the GND terminal. When the measurement probe of the probe unit comes into contact with the sample, the GND terminal comes into contact with the electrode.

The present disclosure relates to a detection system, and, more particularly, to system for detection of passive voltage contrast and methods of use. The system includes a chamber; a stage provided within the chamber, configured to stage a target structure; an electron beam apparatus which is structured to emit an e-beam toward the stage; and a laser source which emits a laser signal toward the stage, at a same area as the e-beam.

The present disclosure relates to a detection system, and, more particularly, to system for detection of passive voltage contrast and methods of use. The system includes a chamber; a stage provided within the chamber, configured to stage a target structure; an electron beam apparatus which is structured to emit an e-beam toward the stage; and a laser source which emits a laser signal toward the stage, at a same area as the e-beam.

A method for analyzing an integrated circuit includes: applying an electric test pattern to the IC; delivering a stream of primary electrons to a back side of the IC on an active region to a transistor of interest, the active region including active structures such as transistors of the IC; detecting light resulting from cathodoluminescence initiated by secondary electrons in the IC; and analyzing the detected light regarding a correlation with the electric test pattern applied to the IC. A system for analyzing an IC is provided.

A method for analyzing an integrated circuit includes: applying an electric test pattern to the IC; delivering a stream of primary electrons to a back side of the IC on an active region to a transistor of interest, the active region including active structures such as transistors of the IC; detecting light resulting from cathodoluminescence initiated by secondary electrons in the IC; and analyzing the detected light regarding a correlation with the electric test pattern applied to the IC. A system for analyzing an IC is provided.

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.

Provided is a method of inspecting a pattern defect. The method includes: applying a voltage to an object to be inspected and measuring an inspection signal generated in a pattern of the object to be inspected due to the voltage applied to the object to be inspected over time; generating an intensity image showing a relationship between an intensity of the inspection signal measured in the pattern and a time by processing the inspection signal; and detecting a pattern defect position by comparing the intensity image with a comparative intensity image.

Provided is a method of inspecting a pattern defect. The method includes: applying a voltage to an object to be inspected and measuring an inspection signal generated in a pattern of the object to be inspected due to the voltage applied to the object to be inspected over time; generating an intensity image showing a relationship between an intensity of the inspection signal measured in the pattern and a time by processing the inspection signal; and detecting a pattern defect position by comparing the intensity image with a comparative intensity image.

An inspection system is provided that includes a microscope that scans a sample with a beam that is an incident electron beam, and an image processing device that controls the microscope. The image processing device performs: an acquisition process of acquiring a plurality of images relating to brightness based on an amount of a signal electron detected from the sample a result of controlling the microscope according to a s and irradiating the sample with the beam, the plurality of image acquisition condition being multiple combinations of different irradiation amounts of the beam per unit length; a first generation process of generating a plurality of actually measured profiles that show a relationship between an irradiation position of the beam in the sample and the brightness of the sample, based on the plurality of images acquired in the acquisition process; and an output process of outputting an electrical contact characteristic of the sample based on the plurality of actually measured profiles generated in the first generation process.

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device.