A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that calculates a frequency at which the characteristic signal reflecting the electrical characteristics of a first layer and the characteristic signal reflecting the electrical characteristics of a second layer have a predetermined phase difference, corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at the scanning position reflecting the electrical characteristics of the first layer as a reference, and outputs an in-phase component and a quadrature component at the arbitrary scanning position at the calculated frequency.

A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics of the semiconductor device; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at a scanning position reflecting the electrical characteristics of a first layer in the semiconductor device as a reference, specifies a phase component of the characteristic signal at a scanning position reflecting the electrical characteristics of a second layer, normalizes the phase component of the characteristic signal at the arbitrary scanning position by using the phase component, and outputs a result based on the normalized phase component.

Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.

Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.

Methods and systems for automated testing of extremely-high frequency devices are disclosed. A device under test (DUT) is set in a simultaneous transmit and receive mode. The DUT receives a lower frequency radio frequency (RF) signal from a test unit and up-converts the lower frequency RF signal to a higher frequency RF signal. The DUT transmits the higher frequency RF signal using a first antenna, and receives the higher frequency RF signal using a second antenna. The DUT down-converts the received higher frequency RF signal to a received test RF signal and provides the received test RF signal to the test unit for comparing measurements derived from the received test signal to a design specification for the DUT.

A system and a method capable of identifying a heat source position corresponding to a failure portion are provided. An analysis system according to the present invention is an analysis system that identifies a heat source position inside a semiconductor device, and includes a tester that applies an AC signal to the semiconductor device, an infrared camera that detects light from the semiconductor device according to the AC signal and outputs a detection signal, and a data analysis unit that identifies the heat source position based on the detection signal.

A system and a method capable of identifying a heat source position corresponding to a failure portion are provided. An analysis system according to the present invention is an analysis system that identifies a heat source position inside a semiconductor device, and includes a tester that applies an AC signal to the semiconductor device, an infrared camera that detects light from the semiconductor device according to the AC signal and outputs a detection signal, and a data analysis unit that identifies the heat source position based on the detection signal.

A method, system, and computer program product for precision probe positioning and testing of an integrated circuit. Methods, systems, and a computer program product implement techniques for determining a particular area of interest for precision probe positioning and testing where the particular area of interest comprises an area less than an entire area of the integrated circuit. Once the particular area of interest for testing has been determined, then a laser probe is steered or otherwise directed to illuminate a plurality of pixels within the area of interest so as to generate reflected signals corresponding to the illuminated pixels. Techniques are provided for measuring the reflected signals to determine information about the IC within the area of interest. CAD data or user data can be used to determine XY addressable pixel locations within the area of interest.