A method for estimating jitter of a clock-signal-under-test includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method includes generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the phase-adjusted clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter estimate using an estimated standard deviation of a distribution of edges of the clock signal based on the N digital time codes for each of the P phase adjustments.

An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

There are provided a vehicle control device and a control method thereof capable of improving safety and reliability with a simple configuration. A vehicle control device 1 that controls a vehicle includes an execution management unit P3 that manages execution of predetermined processing, an execution state recording unit P5 that records a history of execution states of the predetermined processing, and a setting information management unit P4 that manages setting information related to the execution of the predetermined processing. The setting information includes a jitter tolerance which is a tolerance of a jitter. The execution management unit P3 adjusts an execution timing of processing to be adjusted, which is included in the predetermined processing and in which the jitter is generated, based on the jitter tolerance of the processing to be adjusted.

An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A time error vector is determined using pairs of two closest points of input-referred noise data that straddle respective crossing times indicating when a clock signal representation crosses a threshold value, a slew rate of the clock signal representation, and the crossing times. A system filter is applied to the time error vector in the frequency domain. A first RMS value is determined indicating a jitter value present in the filtered time error vector. A raw clock signal time error vector of the clock signal under test is generated, the system filter is applied to the raw clock signal time error vector in the frequency domain, and a second RMS value indicating a jitter content of the filtered raw clock signal time error vector is determined. The second RMS value is corrected using the first RMS value to thereby generate a jitter measurement compensated for input-referred noise.

On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.

A method and system measure a characteristic of a signal under test (SUT) using a signal measurement device. The method includes receiving the SUT through first and second input channels; digitizing first and second copies of the SUT to obtain first and second digitized waveforms; repeatedly determining first and second measurement trends to obtain measurement trend pairs; cross-correlating the first and second measurement trends in each measurement trend pair to obtain cross-correlation vectors; extracting zero-displacement values from the cross-correlation vectors, respectively; summing the zero-displacement values to obtain a sum of measurement products for the measurement trend pairs; divide the sum of zero-displacement values by a total number of measurement products to obtain an average value of the measurement products, corresponding to MSV of the measured SUT characteristic; and determining a square root of the average value of the MSV to obtain an RMS value of the measured SUT characteristic.