A measurement device comprising a measurement unit adapted to measure a transmission characteristic for providing an eye pattern; and a conversion unit adapted to convert automatically the eye pattern into a character separated values, CSV, file.

The invention relates to a method as well as an apparatus configured for its execution for monitoring the reliability of an electronic system, in particular an electronic system comprising one or more electronic components. The method comprises: repeatedly measuring, at different measurement times and according to a predetermined transmission quality measure, a transmission quality of signals transmitted to or from the electronic system over a wired electrical signal transmission path; (ii) comparing, for each of the measurement times, the associated measured transmission quality with a respective associated transmission quality reference value previously determined according to the transmission quality measure; and (iii) determining a value of a reliability indicator associated with the respective measurement time in dependence on the result of the associated comparison In this regard, the transmission quality measure is defined as a measure of the extent of a subrange of a one- or multi-dimensional operating parameter range of the electronic system in which, according to a predetermined reliability criterion, the electronic system operates reliably.

It is possible to know a guideline for adjusting the levels of three voltage thresholds of a PAM4 signal. An error detection device receives a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels, decodes the measurement pattern into a most significant bit sequence signal MSB and a least significant bit sequence signal LSB, based on three voltage thresholds Vth1, Vth2, and Vth3, identifies and counts, by a level counting unit, the four levels of the measurement pattern, based on the most significant bit sequence signal MSB and the least significant bit sequence signal LSB, and displays numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern so as to be in the same order as waveform levels of the measurement pattern, based on a result of the counting.

A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

A margin testing device includes at least one interface structured to connect to a device under test (DUT) one or more controllers structured to create a set of test signals based on a sequence of pseudo random data and one or more pre-defined parameters, and an output structured to send the set of test signals to the DUT. Methods and a system for testing a DUT with the disclosed margin tester and other testing device are also described.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.

Various embodiments provide for testing a transmitter using a phase-lock loop, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer using a sample clock signal generated by an M/N phase-lock loop (PLL); and using a pattern checker to error check the sampled data to determine whether the data transmission test passes.