A signal generator includes inverse characteristic calculation means for calculating an inverse characteristic of a transfer function from an inverse characteristic of a frequency characteristic of a signal based on the transmission standard, inverse Fourier transform means for calculating impulse responses of a plurality of points by performing inverse Fourier transform on the inverse characteristic of the transfer function, impulse response cutout means for cutting out the points for a predetermined number of taps from the impulse response, frequency characteristic calculation means for calculating a frequency characteristic based on values of the points for the number of taps cut out from the impulse response, and display control means for displaying on a display screen, the frequency characteristic calculated by the frequency characteristic calculation means and an ideal frequency characteristic read from an S parameter file of a device under test.

A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.

A test instrument may include a transmitter configured to transmit signals to a unit under test, a receiver configured to receive signals from the unit under test, and a controller configured to generate a transmitter compensation filter by (i) transmitting, with the transmitter, complex multi-sine signals over a first plurality of observed frequencies within a predetermined baseband frequency range, (ii) estimating a first plurality of frequency responses that compensate for in-phase and quadrature (IQ) imbalance at the first plurality of observed frequencies within the predetermined baseband frequency range, and (iii) determining, using the first plurality of frequency responses, a transmitter polynomial surface, and to compensate, using the transmitter compensation filter, at least one of the signals to be transmitted by the transmitter to reduce IQ imbalance in the transmitted signals, including using the transmitter polynomial surface to calculate a frequency response that reduces the IQ imbalance in the transmitted signals.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

An error rate measurement apparatus includes a display control unit, an operation display unit, and a control unit. The display control unit displays a firsts coefficient value in a selectable manner by tabs of a number corresponding to a Full Swing value, performs matrix display on a display screen by using each one of combinations of each second coefficient value and each third coefficient value in the first coefficient value on the selected tab, and displays each coefficient value on the display screen in a three-dimensional bird-eye view by using each second coefficient value and each third coefficient value as a combination of a horizontal direction coordinate axis and a vertical direction coordinate axis and using the first coefficient value as a depth direction coordinate axis. The operation display unit selects a range including at least one cell as a scanning target in the matrix display or a bird-eye display.

Methods and systems for determining and calibrating non-linearity in a phase interpolator. Embodiments determine a first jitter value that causes the bit error rate (BER) of a data sequence to exceed a predefined target BER, when a recovered clock is aligned with the data sequence at a first PI code. The recovered clock is obtained from a data pattern representing the data sequence. Embodiments determine a second jitter value that causes the BER of the data sequence to exceed the predefined target BER at a second PI code. The first PI code may immediately precede or succeed the second PI code. Embodiments determine a Differential Non-Linearity (DNL) corresponding to the second PI code, based on a phase shift introduced to the recovered clock by the second PI code relative to the first PI code, the first jitter value, and the second jitter value. All DNL values corresponding to all PI codes may be determined in a similar manner. An Integral Non-Linearity (INL) may be determined by integrating the DNL corresponding to all PI codes.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.