The testing of a received data signal accessed from a device under test. Communication circuitry first generates an instruction that causes the device under to emit the data signal towards quality parameter contour generation circuitry. The contour generation circuitry is then configured to generate quality parameter (e.g., bit error ratio) contour of the data signal, which is then received at the contour generation circuitry. The generated contour map may then be evaluated to diagnose the performance of the device under test in emitting the data signal. For instance, each device under test may be evaluated after manufacture. The quality parameter contour generation circuitry may be embedded within an electronic device, such as a consumer electronic device. A diagnostic component within the electronic device is configured to use the quality parameter contour generated by the contour generation circuitry to self-test the device.

An eye-diagram index analytic method includes: calculating a transfer function of multiple coupled lines; converting the transfer function into a pulse response; calculating an eye-diagram index according to the pulse response; and correcting the eye-diagram index according to peak distortion analysis.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.