A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

A multi-channel device with a single diagnosis status pin may be configured to detect if one or more channels has a fault. The multi-channel device, which may operate within a system, can communicate which channel, of a plurality of channels, has the fault using only a single diagnosis status pin and no additional diagnosis control pins. The multi-channel device may output a fault signal on the diagnosis status pin and in response to an interrogation input signal on the same channel as a fault channel indicate to the system which channel is the fault channel.

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customer's system using the device. Additional embodiments are also provided and described in the disclosure.

A device comprising includes an output terminal and a first current path from the output terminal to a first reference voltage. The first current path includes a series connection of current electrodes of a first transistor and a second transistor. The first transistor receives at a control electrode a signal to set a desired level of current to be conducted by the first current path. The second transistor generates at a control electrode a feedback signal indicative of an actual current conducted by the first transistor.

A testing system includes a subtractor and a divider. The subtractor is configured to receive a first voltage of a circuit being tested and a second voltage of the circuit, and to derive a difference between the first voltage and the second voltage. The divider is configured to receive the difference between the first voltage and the second voltage, and to derive a resistance of the circuit by dividing (i) the difference between the first voltage and the second voltage by (ii) a difference between a first current applied to the circuit and a second current applied to the circuit. The first voltage is corresponding to the first current, and the second voltage is corresponding to the second current.

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

A port manager is configured to implement adaptive port ceiling assignment for background Input/Output (I/O) operations between heterogeneous storage arrays. The port manager generates a set of test I/O operations, applies the I/O operations to a port under test, determines a response time to complete the I/O operations on the port under test, and compares the response time of the current test with response times of a set of previous tests. Based on the test values, the port manager identifies a throughput inflection point for the port under test, which is used to set a maximum throughput of the port under test. The adaptive ceiling for the port under test is then set based on the maximum throughput times a ceiling percentage threshold value. The determined adaptive ceiling value is then used to prospectively limit background I/O operations on the port under test.

The present disclosure relates to a controller area network, CAN, transceiver, comprising: a transmit data, TXD, interface, a receive data, RXD, interface, a CAN Bus interface, a transmitter, a receiver, a reducer, and a test unit, wherein the transmitter is coupled between the TXD interface and a test unit input of the test unit, a first test unit output of the test unit is coupled to the CAN Bus interface, the CAN Bus interface is coupled to a receiver input of the receiver via the reducer, a second test unit output of the test unit is coupled to the receiver input of the receiver, the test unit is configured, in a first state, to couple the test unit input to the first test unit output and is configured, in a second state, to couple the test unit input to the second test unit output.

A test device includes a data driver and a controller. The controller is configured to generate a test code by dividing a test sequence in a unit of n-bits. The data driver is configured to receive the generated test code and output one of input voltages to a device under test as a test signal based on the generated test code. A storage device stores a test sequence.